Note: I using quartus ii v13 with vhdl 2008

I am trying to access the current state of my state machine from inside my test bench file. From my understanding I should be able to do this with External Names, however, I keep getting a syntax error "near text "<"; expecting an identifier, or string literal"


library ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

entity GFI_entity is
   port (
      CLK            : in  std_logic;   
      my_input1      : in  std_logic;
      my_input2      : in  std_logic;
      RST            : in  std_logic;

      my_output1     : out std_logic;
      my_output2     : out std_logic;
      my_output3     : out std_logic
end GFI_entity;

architecture rtl of GFI_entity is

constant C_2SEC_TC : integer := 127; -- Set this based on clock speed to get desired time 

type machineState is (state1, state2, state3, state4, state5, state6, off_state);

signal currentState, nextstate : MachineState;
signal tmr_cnt  : std_logic_vector(6 downto 0); -- time counter
signal tc_2sec  : std_logic := '0'; -- Indicates counter has reached desired time
signal rst_flag : std_logic := '0'; -- Disables RST if test pulse was successful
signal tmr_exp  : std_logic := '0'; -- Latches state of tc_2sec

alias myalias is <<signal .GFI_entity_tb.GFI_entity.currentstate : machinestate>>;


   -- synchronous process for the state machine
   sm_sync_proc: process(CLK, RST, rst_flag, tmr_exp)
        -- condition for RST to not cause a reset if test was successful or timer expired
        if((rst_flag = '1' or tmr_exp = '1') and RST = '0') then
            currentstate <= off_state;
        elsif(RST = '0' and tmr_exp = '0') then
            currentState <= state1;
        elsif(rising_edge(CLK)) then
            currentState <= nextstate;      
        end if; 
   end process sm_sync_proc;
cominationLogic: process(currentState, nextstate, my_input1, my_input2, tc_2sec, RST, rst_flag)


  case currentState is
    -- Wait for charge up time of all inputs
     when state1 => 


USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;

ENTITY GFI_entity_tb IS
END GFI_entity_tb;

ARCHITECTURE behavior OF GFI_entity_tb IS 

-- Component Declaration for the Unit Under Test (UUT)

PORT(   my_input1     :   in    std_logic;
        my_input2     :   in    std_logic;
        RST           :   in    std_logic;
        clk           :   in    std_logic;

        my_output1    :  out    std_logic;
        my_output2    :  out    std_logic;
        my_output3    :  out    std_logic


signal my_input1 : std_logic := '0';
signal my_input2 : std_logic := '0';
signal RST       : std_logic := '0';
signal clk       : std_logic := '0'; 

signal my_output1 : std_logic;
signal my_output2 : std_logic;
signal my_output3 : std_logic;
signal count      : std_logic_vector(2 downto 0) := "000";

--Clock for testing
constant clk_period : time := 2 ms; -- 500Hz

-- Instantiate the Unit Under Test (UUT) 
uut: GFI_entity PORT MAP (
     my_input1 => my_input1,
    my_input2 => my_input2,
     RST => RST,
     clk => clk,

     my_output1 => my_output1,
     my_output2 => my_output2,
     my_output3 => my_output3               

 Clk_process: process
    clk <= '1';
    wait for clk_period/2;
    clk <= '0';
    wait for clk_period/2;
end process;

-- Stimulus process
stim_proc: process
*do testing here*

How can I correctly use External Names here to access my currentstate signal?

The purpose of me wanting to do this is that in my test bench I want to be able to test all possible input conditions at each state, for all my states.

Say im in state2 of my test bench and I want to test a certain input, say input1 = 0 input2 = 1 RST = 0, my state machine should change states. After it does I want to "reset" my current state to be my previous state, state2, so that I can check other possible inputs for state2.

I plan for my test bench to just be a for loop from input1 = 0 input2 = 0 RST = 0 to input1 = 1 input2 = 1 RST = 1, after each iteration of the for loop wait for it to change states, "reset" the current state, and do this 8 times for each state. So that if I have 8 states and 3 inputs it will have tested 64 different combinations. Simply put, I want to test all possible cases.

Maybe theres an easier way to do this? This is my first test bench I've done.


  • \$\begingroup\$ Is machinestate defined in a package? If not, then the type will not be known in your testbench. You have two choices: 1) move machinestate to a package or 2) access an integer equivalent signal - machinestate'pos(stateval) \$\endgroup\$
    – Jim Lewis
    Sep 25 at 1:37

Two things right off the bat:

  • If you want to use myalias in the testbench, that's where you need to declare it.
  • You need to use instance names in the external name path, not the entity names. For example, <<signal uut.currentstate : machinestate>> (path relative to GFI_entity).

But I don't see why you're getting that specific error message.

Related question: How to bring out internal signals of a lower module to a top module in VHDL?

  • \$\begingroup\$ I don't see why you're getting that specific error message Quartus II which is VHDL -1993 compatible doesn't support external names, a -2008 feature. \$\endgroup\$
    – user8352
    Sep 13 '19 at 21:24
  • \$\begingroup\$ @user8352 In the settings of Quartus ii I have checked VHDL 2008 under version \$\endgroup\$
    – Sean Kerr
    Sep 13 '19 at 21:33
  • \$\begingroup\$ External names aren't synthesis eligible. Don't submit your testbench to synthesis. \$\endgroup\$
    – user8352
    Sep 13 '19 at 21:56
  • \$\begingroup\$ @user8352 Thank you, I did not know that! Do you know the appropriate external path name in my case? Would it be GFI_entity.currentstate as the signal im trying to access is in the GFI_entity architecture? \$\endgroup\$
    – Sean Kerr
    Sep 13 '19 at 22:11

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