Note: I using quartus ii v13 with vhdl 2008
I am trying to access the current state of my state machine from inside my test bench file. From my understanding I should be able to do this with External Names, however, I keep getting a syntax error "near text "<"; expecting an identifier, or string literal"
library ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; entity GFI_entity is port ( CLK : in std_logic; my_input1 : in std_logic; my_input2 : in std_logic; RST : in std_logic; my_output1 : out std_logic; my_output2 : out std_logic; my_output3 : out std_logic ); end GFI_entity; architecture rtl of GFI_entity is constant C_2SEC_TC : integer := 127; -- Set this based on clock speed to get desired time type machineState is (state1, state2, state3, state4, state5, state6, off_state); signal currentState, nextstate : MachineState; signal tmr_cnt : std_logic_vector(6 downto 0); -- time counter signal tc_2sec : std_logic := '0'; -- Indicates counter has reached desired time signal rst_flag : std_logic := '0'; -- Disables RST if test pulse was successful signal tmr_exp : std_logic := '0'; -- Latches state of tc_2sec alias myalias is <<signal .GFI_entity_tb.GFI_entity.currentstate : machinestate>>; begin -- synchronous process for the state machine sm_sync_proc: process(CLK, RST, rst_flag, tmr_exp) begin -- condition for RST to not cause a reset if test was successful or timer expired if((rst_flag = '1' or tmr_exp = '1') and RST = '0') then currentstate <= off_state; elsif(RST = '0' and tmr_exp = '0') then currentState <= state1; elsif(rising_edge(CLK)) then currentState <= nextstate; end if; end process sm_sync_proc; cominationLogic: process(currentState, nextstate, my_input1, my_input2, tc_2sec, RST, rst_flag) begin case currentState is -- Wait for charge up time of all inputs when state1 => ...
LIBRARY ieee; USE ieee.std_logic_1164.ALL; use ieee.numeric_std.all; use IEEE.std_logic_unsigned.all; ENTITY GFI_entity_tb IS END GFI_entity_tb; ARCHITECTURE behavior OF GFI_entity_tb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT GFI_entity PORT( my_input1 : in std_logic; my_input2 : in std_logic; RST : in std_logic; clk : in std_logic; my_output1 : out std_logic; my_output2 : out std_logic; my_output3 : out std_logic ); END COMPONENT; --Inputs signal my_input1 : std_logic := '0'; signal my_input2 : std_logic := '0'; signal RST : std_logic := '0'; signal clk : std_logic := '0'; --Outputs signal my_output1 : std_logic; signal my_output2 : std_logic; signal my_output3 : std_logic; signal count : std_logic_vector(2 downto 0) := "000"; --Clock for testing constant clk_period : time := 2 ms; -- 500Hz BEGIN -- Instantiate the Unit Under Test (UUT) uut: GFI_entity PORT MAP ( my_input1 => my_input1, my_input2 => my_input2, RST => RST, clk => clk, my_output1 => my_output1, my_output2 => my_output2, my_output3 => my_output3 ); Clk_process: process begin clk <= '1'; wait for clk_period/2; clk <= '0'; wait for clk_period/2; end process; -- Stimulus process stim_proc: process begin *do testing here*
How can I correctly use External Names here to access my currentstate signal?
The purpose of me wanting to do this is that in my test bench I want to be able to test all possible input conditions at each state, for all my states.
Say im in state2 of my test bench and I want to test a certain input, say input1 = 0 input2 = 1 RST = 0, my state machine should change states. After it does I want to "reset" my current state to be my previous state, state2, so that I can check other possible inputs for state2.
I plan for my test bench to just be a for loop from input1 = 0 input2 = 0 RST = 0 to input1 = 1 input2 = 1 RST = 1, after each iteration of the for loop wait for it to change states, "reset" the current state, and do this 8 times for each state. So that if I have 8 states and 3 inputs it will have tested 64 different combinations. Simply put, I want to test all possible cases.
Maybe theres an easier way to do this? This is my first test bench I've done.