# STM32: SPI hardware to implement custom serial interface

I want to implement SDLC communication on an STM32 (assume I can pick any one up to M7) using the existing HW in it.

SDLC is a full duplex synchronous serial interface. In my case, it uses differential signaling (RS-485), so I am using some MAX488 to convert the differential signals to single ended signals.

So I have Tx Clock and Data, Rx Clock and Data.

I was thinking about using one SPI as master for transmitting the data and one SPI as slave for receiving the data.

A few questions:

1. Is this possible? Is there any better way to achieve this with only an STM32?
2. How can I generate 153.6 and 614.4 kHz clocks for SPI Tx?
3. Can the SPI slave receive any clock? Like 614.4 kHz?

assume I can pick any one up to M7

Then pick one from STM32H7 series, it has direct hardware support for all the features you need for this, independent fractional PLL to generate arbitrary SPI clock rates, and variable frame length if you need bit stuffing, i.e. frame length is not necessarily a multiple of 8 bits.

Any other STM32 can do it as well, even the smallest ones, but some tricks would be needed, like looping back a timer output externally to the SPI clock input, as they have only a simple power-of-two prescaler for SPI clock generation.

Any better way to achieve this with only an STM32?

I can't think of any.

How can I generate 153.6 and 614.4 kHz clocks for SPI Tx?

Experiment with the clock tree configurator in STM32CubeMX to understand how it works (faster than by reading the reference manual), get PLL2 or PLL3 to output 0.1536*256=39.3216 MHz and map it to the SPI clock. Then use the prescaler in the SPI peripheral to get 153.6 kHz (/256) or 614.4 kHz (/64).

I'm quite certain that a better match is possible by fiddling with the divisor and multiplier values.

Can the SPI slave receive any clock? Like 614.4 kHz?

Any clock up to the limit in the datasheet, which is usually in the tens of MHz range. There is no low limit.

• I found a STM32H750VBT6 which has an amazing price of less than 7 dollars for moq 1. What about if I wanted to cost optimize this? The only problem I have is generating the clock signal because a non h7 doesn't have a fractional PLL? – Uriel Katz Sep 14 '19 at 16:32
• It can be approximated with a plain PLL, so what is the tolerance of the clock frequency? The other problem would be if there is bit stuffing or NRZI encoding which would result in frame lengths that are not a multiple of 8 bits. Can we assume that each byte is represented as 8 bits on the wire or not? – followed Monica to Codidact Sep 14 '19 at 17:56
• There may be an issue with the SPI slave since the SS line is generally used to clock the bits into the read register. – Caleb Reister Sep 14 '19 at 18:48
• @berendi - for SPI tx, my current code takes care of it even though there is NRZI. for SPI rx right now it is using a interrupt on the RxC which samples the RxD, it can be changed to take into consideration 8 bits but it is going to be a PITA. So I think I will stay with an STM32H7 for now – Uriel Katz Sep 15 '19 at 11:13
• @CalebReister - can I just tie the SS line to ground so the SPI salve is always "selected"? – Uriel Katz Sep 15 '19 at 11:15