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I'm confused about the via placement in power traces either to change layers as part of routing the main supply or to get to component pins from a layer different to where the power trace is located, and from components such as decoupling caps to the ground reference plane.

I read here "Many small via vs few bigger via" and here "https://www.ultracad.com/articles/viacurrents.pdf" that having multiple vias is better but both sources talk more about the thermal benefits of having multiple small vias as opposed to one big via.

My confusion is when I look at this from an inductance standpoint since small vias have higher inductance and high inductance is definitely not a good idea in a power distribution network.

So my questions are. Is it better to have two, or more, 10 mil vias or one large 30 mil or 40 mil via on decoupling capacitors?

Vias for decoupling caps

And, is it better to have multiple 10 mil vias or one large via to connect VCC top layer to bottom layer and the power supply GND to the GND plane?

PDN multiple small vias PDN one lagre via

I'm not concerned about the heat but more for power integrity. I just want to be able to switch layers without introducing much inductance and have effective decoupling.

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    \$\begingroup\$ putting several inductors in parallel produces a lower inductance, same as with resistors in parallel, \$\endgroup\$
    – Jasen
    Sep 15, 2019 at 4:34
  • \$\begingroup\$ So that would mean that is essentially the same to put multiple small vias or one large via, right? \$\endgroup\$
    – m4l490n
    Sep 15, 2019 at 4:36
  • \$\begingroup\$ I would think so, but I have not seen any numbers. \$\endgroup\$
    – Jasen
    Sep 15, 2019 at 4:38
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    \$\begingroup\$ @Jasen is mostly correct, but remember that multiple vias near each other will have mutual inductance, which will make the usual parallel inductors formula (\$1/L_{eq}=1/L_1+1/L_2+...\$) somewhat optimistic. Despite this I would still expect multiple small vias to come out better than one big via in cases where the small vias provide lower resistance than the big via. \$\endgroup\$
    – The Photon
    Sep 15, 2019 at 5:27
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    \$\begingroup\$ what is the load? In general for 3.3V rail no need to taken this much considerations unless specific transients on this rail. Yes, Multiple vias connecting a plane is better than single big Via. Clustering(maintaining close proximity of vias with x and y between via's kept constant and minimum) of Via's also very important, otherwise vias won't share currents symmetrically. \$\endgroup\$
    – user19579
    Sep 17, 2019 at 4:24

2 Answers 2

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Many small vias are better. Consider this configuration:

vias

source

The measured inductance, as given in the source, is (nH) 0.61, 1.32, 2.00, 7.11, 15.7, and 10.3 for configuration A, B, C, D, E, and F respectively.

The reason for that is that via inductance increases slightly when the diameter is decreased. This is more than compensated for by having multiple vias in parallel. There are many approximations for the via inductance you can use to validate the above result, such as

$$L = 5.08 h \left( \ln \frac{4h}{d} + 1 \right) 10^{-9}.$$

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Remember that the connection is made by the plating of the inside of the holes, so that on a board with two mils of plating in the vias, the current must flow through a tube with a two-mil wall thickness on the inside of your hole, possibly to a one-mil trace that touches only on the edge of the tube (if the hole was cleanly drilled, but that is a whole different topic). In your example, the nine 10-mil vias would have more copper cross section through the board than the one 50-mil via (roughly 9:5). This is important both for resistance at high currents and for skin effect at high frequencies.

The other consideration is cracking, especially when connecting to internal layers. Copper expands at a different rate than FR4 or other board material, so there will be more differential movement, and more stress, as the geometry gets larger if the board is cycled at temperature. Similarly, when the board is flexed during vibration or handling, a larger geometry means that the stress is greater on the joint between the hole plating and the trace.

For external layers only or two sided boards, I have seen single large vias with a piece of bus wire through and soldered on both sides for high power, but multiple small vias are usually better if you are dependent on the plating to carry the current.

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  • \$\begingroup\$ At this point, I'm more concerned about power integrity than current and thermal capabilities, I mean, having a clean supply with low inductance for all the digital circuitry in the board. By the majority of the comments, it's clearer now that many small vias are better than one big one from a current perspective. \$\endgroup\$
    – m4l490n
    Sep 17, 2019 at 1:30

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