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I programmed a full adder in VHDL as shown in the picture below: enter image description here

However, when compiling it, I get the following diagram when I open the Technology Map Viewer: enter image description here

My compilation report also says that I have a total of 2 logic elements. I tested the second circuit, which indeed is also a full adder when comparing it to a truth table.

Any idea why the compiler does this and what the advantage is?

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  • \$\begingroup\$ Just look at the diagram and think - clearly it performs the same logical function. \$\endgroup\$
    – Andy aka
    Sep 16, 2019 at 11:03

1 Answer 1

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You didn't say, but I'm guessing that your target technology is an FPGA.

Most FPGAs implement logic by using LUTs (look-up tables) — small pieces of memory that can implement arbitrary functions of 4, 5 or 6 variables (depending on the specific FPGA). A "logic element" is usually a combination of a LUT, a flip-flop, and some other miscellaneous logic.

Therefore, since you have only the two outputs and three inputs, the synthesis tool (compiler) uses one LUT for each of the outputs, and the actual function implemented in each LUT is represented by the logic in each of the blue boxes. But in the actual hardware, each one is just a string of 8 bits (1s and 0s) that represent the function value for every combination of the input values.

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