# How to measure or estimate the phase delay between two analog input channels of this board?

There is a 16-bit data acquisition board with +/-10V range which multiplexes analog inputs and buffers the data to the PC. Specifications are given here (DAS6036 is the model in question).

Now I need to quantify by measuring or estimating the phase delay between two analog inputs of two channels. The board seems like have one A/D converter which is multiplexed between channels because under the key features sampling is mentioned as multiplexed. More detail for the board is given here.

First I wanted to measure the delay at 100Hz sampling between Ch0 Ch7 and Ch13. To do that I set the function generator to a 1Hz sine wave and splitted the the function generator's output to three by using three same length coax cables and coupled them to Ch0, Ch7 and Ch13.

Below shows 5 seconds of logged data:

And here if we zoom it we can observe the delay between the channels:

Now the function generator output is set to 1Hz triangular wave and sampling frequency is again 100Hz(we cans still observe the delay):

But now keeping the same input if I increase the sampling rate to 4kHz I cannot observe that delay anymore:

By increasing the sampling rate I was hoping to observe the delay is being reduced. But as you see the the delay is kind of buried in noise.

Here are the questions I couldn't figure out:

1. What could be happening here which makes us impossible to observe the phase delay? Is there a better setup or method to measure such delay at higher sampling frequencies?

2. If we cannot measure, is it enough to estimate the phase delay by using the specs? Here is an excerpt from this site:

How can I conclude the board in question is Pseudo Simultaneous or Evenly Spaced?

While the resultant phase shift is probably down to the multiplexer, this can be calculated from the data you have.

Since the waveforms will be of equal frequency, you can multiply any two of the signals together and low-pass filter (or moving average) the resultant signal to extract the phase difference.

Extracting phase-shift and gain from a time series information

• This is also very interesting. I will try this tomorrow when I have the access. Is there a rule of thumb low pass filter cut off? If the input signal is 1Hz what would be the LP filter cut off set? Or does that depend the noise? Thanks Sep 17, 2019 at 1:15
• is this to post-process (ie you have the data as a CSV)? if so it is better todo a moving average filter with a sample depth equal to your period. If you don't want to do this or this is in real-time then its a matter of setting the LPF. This method shifts the frequency to twice: 1Hz -> 2Hz. You need a filter that attenuates this quite significantly so it could be a 3dB at 0.2Hz. However... if you are expecting phase oscillations you might need to increase the cutoff to capture this. Then its a matter of 2nd, 3rd etc.... Worst case go for the quad-freq method
– user16222
Sep 17, 2019 at 8:32

The observed phase delay is artificial, caused by delay in round robin sampling due to multiplexer reconfiguration and sample settling time, it is an artifact of software they are given same time stamp. A better sampling system would offset time stamps.

As you increase sampling frequency, the phase delay shrinks when in "evenly spaced" sampling mode.

In "psuedo simultaneous" mode you would expect sample delay to stay consistent, as such we can conclude the internal sampling is evenly spaced but you are pushing the device to it's maximum rate such that the difference disappears.

In this case there is nothing better to go on besides the published specification and calculating the phase offset yourself (by adjusting the time stamp)

In psuedo simulatenous mode you always sample at the fastest rate, or at a rate much faster than your programmed sample rate, and then wait until the next sample period, this is done at expense of noise in order to get better synchronization.

The other approach, "evenly spaced" sampling is to set the sample rate multiplied by the number of channels better noise performance, but at expense of synchronization.

As you increase the programmed sample rate these two approaches lose their difference, because you cannot sample faster than the fastest rate, at some point the "evenly spaced" internal periods become as wide as the "psuedo-differential" internal periods.

It is also possible the device switches in modes when sampling rate passes a threshold

Since you are measuring internal phase offset, it is not really easy to measure ones own delay to a better degree than you have, certainly you can compare with another ADC sampling without channel cycling.

• "As you increase sample rates these two become the same." What two becomes the same? And what do you mean by "8x your intended rate"? Do you mean I should set the sampling rate to 8 times the input signal freq? Sep 17, 2019 at 0:59
• I am refering to the difference between the two sampling modes you mention in your question, at some point when you push the sample rate very high, the even spacing may become as short as the psuedo-differential spacing. I edited the answer to be clear. You need to post adjust in software to correct the delay or sample at the fastest rate and do software averaging to cut the noise its a balanced equation of sorts. Sep 17, 2019 at 1:06
• Sorry being dumb but "to set the sample rate multiplied by the number of channels". Could you clarify this a bit more with this example of mine here: If the input signal is 100Hz and the sampling rate is 4kHz? What should I do if the number of channels are 16? Sep 17, 2019 at 1:10
• @panicattack assuming you cannot control the internal behavior of this acquisition product, this is a detail hidden from you. As such you need to post-process your data, either shift time stamps to correct for ADC delays, or sample at the fastest rate and average to get better noise. You can only control the macroscopic sample rate, the tool you are using may hide how it configures the round robin sampling. Sep 18, 2019 at 20:18