I am looking for information on JTAG interface on PCI-e 1x connector. Do anyone has an informaton how to program it? I would like to use it to program microcontrollers and FPGAs.
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\$\begingroup\$ I suspect you will find that this is a theoretical possibility but not something typically implemented in practice. You'd likely be better off with something like an FT2232 hanging off a USB port, or a target-specific adapter. \$\endgroup\$– Chris StrattonSep 17, 2019 at 3:09
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\$\begingroup\$ If I understand well, this lines are in the are, nor "ring" from where I can read test data? That sound completly stupidity add 5 line for nothing. I am searching the net over 10 hours and no results how can I access the "ring" buffer. \$\endgroup\$– RedDragonSep 17, 2019 at 9:53
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3 Answers
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JTAG interface in PCIe connector is optional as per PCI-SIG. They won't define any specifications for these pins. They are defined as per 1149.1.
You have not specified this question in the perspective of addin card or host.
If you want to program devices on JTAG inside Add-in card from Host, then connect this pins to PCIe connector and see support in host side for programming this.
Below is the snap from CEM
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\$\begingroup\$ I have found this lines but how I can control the "ring"? ICH8 i965 or where is the register for the ring buffer? \$\endgroup\$ Sep 17, 2019 at 9:56
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\$\begingroup\$ I read detailes of the aboves. HP is responsible to build-up the "ring" system? I am a little conserned and I hope in God help they did it for their own testing purposeses and after this long periode they publish it. It would make from old unvaluable electrical to a great computer for a further 10's of years. \$\endgroup\$ Sep 17, 2019 at 10:20
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\$\begingroup\$ The SuperIO is containes confidential part, which may containes JTAG as in the case on an other IO. It would be great HP cooperating with Microchip open this confidential part of the SCH5317-NS. I think this more than 15 years old machines out of important orders, but would be great opportunity for enthusians. Also image of HP could improve and great computers could formed. \$\endgroup\$ Sep 17, 2019 at 11:56
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While the PCIe connector does have a few pins designated for JTAG, they are virtually never used. In particular, they are never connected to anything on PC motherboards.
If you want to program devices over JTAG, you will need to purchase a JTAG adapter -- these are typically USB devices. The JTAG functionality defined on the PCIe connector will not be of any help to you.
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The PCIe JTAG doesn’t have a specific usage definition, nor is it required in the interface. In theory it could be used for board test and programming.
As a practical matter it’s much easier to provide specific JTAG connectors as needed for your application, e.g., microcontroller debug, FPGA programming and such. This kind of approach also avoids signal integrity issues that often bedevil large JTAG daisy-chain routing setups.
answered Sep 17, 2019 at 3:26
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\$\begingroup\$ What you have claimed here is factually false. There is in fact, a specific definition. It is probably all but never implemented, it is probably a bad idea, but it is defined. \$\endgroup\$ Sep 17, 2019 at 3:32
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1\$\begingroup\$ It is only defined inasmuch as there are a few pins designated for JTAG functionality. Any JTAG TAP that sits behind that, however, is not defined by PCI-SIG. \$\endgroup\$– user39382Sep 17, 2019 at 3:34
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\$\begingroup\$ Why would PCI-SIG redefine what has already been defined by the Joint Test Action Group? How a controller (if present) talks to devices is clear; what they chose to say to each other, is as it always is largely device specific. The practical issue is not a lack of definition, it is a lack of implementation. \$\endgroup\$ Sep 17, 2019 at 3:52
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1\$\begingroup\$ And therein lies the problem. Its use in a standard platform never gelled with a well-defined purpose. There’s nothing keeping edge-finger JTAG from using used for board test, but that use case tends to have a different architectural scheme with multiple connections to the fixture to reduce test time and increase coverage. As far as programming the board, there’s better ways to do that: SMBus for small stuff, and PCIe itself for bigger stuff (e.g., tandem config for FPGA.) Finally, JTAG at large scale is very twitchy, SI-wise. It’s just not worth the trouble to stitch together multi boards. \$\endgroup\$ Sep 17, 2019 at 4:39
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\$\begingroup\$ Actually, PCIe signals are unique to each slot, not shared. \$\endgroup\$ Sep 17, 2019 at 4:53