I have a piece of test gear I am working on designing, in which there I need to drive a number of N channel mosfets, (3 high side, 2 low side)

I found there is a very large range of gate drivers intended for driving 3 phase motors, and thought this would be a good option as it would provide the drivers I need in a cheap, & space efficient package.

The design I ended up using was the Allegro A4919GETTR-3-T to drive NTMFS4C029N mosfets.

I am roughly aware of how the bootstraping circuit works, and the limitations it places on maximum on time. However I expected be able to generate longer than I am. I would like to be able to generate pulses at least 200ms long, but with the current setup only seem to be able to manage about 5ms before the Bootstrap voltage monitor kicks in.

I am running with a 15V supply, and my bootstrap capacitors are 0.1uF

Searching through the datasheet I did find "GHx Passive Pull-Down Resistance" specified at 400kΩ this seems pretty low to me but would potentially explain my problem.

I assume this property is intrinsic to the device and cant be changed, is there anything I can do to increase my maximum on time.

The only thing I can think of is increasing my bootstrap capacitor size(and correspondingly Vreg capacitor). However I don't know what controls the sizes I can use, can I just throw a 20uF capacitor in and call it a day or will this fry the bootstrap diode.

As a further down the road backup option (requiring a PCB redesign) what factors would need to be considered before switching to something like a TMC6200 with an integrated charge pump to allow 100% on time operation.

  • \$\begingroup\$ Low side PWM must exceed frequency where Z(cap) << R \$\endgroup\$ Sep 17, 2019 at 8:55
  • \$\begingroup\$ (From memory): The datasheet provides explicit formulas for calculating bootstrap capacitors and holdup time. What results do you get when you use these as a design guide? \$\endgroup\$
    – Russell McMahon
    Sep 19, 2019 at 10:45
  • \$\begingroup\$ I already went larger than the design guide, but couldn't see anything in the notes about holdup time. I suppose I want to know how high I can go on the capacitance without damaging the bootstrap diode. \$\endgroup\$
    – Hugoagogo
    Sep 19, 2019 at 10:58

3 Answers 3


Before increasing the size of the caps I would check their capacitance at the voltage you are using them. In several cases, the change in the capacitance values with the bias DC voltage can be massive! Check this page to get a better idea of the phenomena.

Now if that is not the issue, I think that increasing the size of the capacitor will be the most reasonable option. If you are afraid of burning the bootstrap diode, you can include a small resistor in series with the cap. I have seen some designs with this modifications and they work fine.


If you want to generate 200 ms pulses, I would suggest two things:

  1. Use TLP350 type of optocoupler with isolated power supply with each optocoupler. In this way you can generate longer pulses. Because it works in a different way.

  2. Use low ESR capacitors like tantalum capacitors connected in parallel with your current setup. You can use 10uF 16 volt capacitors in parallel.


Some tips on how to design a boot-strapped power supply rail:

The charge available to hold-up the boot-strapped power rail is determined by:

  1. The boot-strap capacitor nominal capacitance value.
  2. The supply voltage during capacitor re-charge.
  3. The degree to which the charge stored in the capacitor reduces as voltage increases, this is dependent on the type of capacitor selected, and its capacitance vs DC bias characteristic.
  4. The amount of charge transferred into the boot-strap capacitor during re-charge via the boot-strap diode.
  5. The minimum voltage permitted at the boot-strapped rail, ie: how low this voltage can go before affecting the intended operation of the circuit.
  6. The amount of charge removed from the capacitor during discharge, ie: the load connected at the boot-strapped rail.

More detail for Item 4: The minimum value of this is determined by:
(a) the shortest on-time of the lower power switch (this is the switch that, when turned on, causes the boot-strap capacitor to re-charge).
(b) the voltage available to drive the charging current, be sure to take into consideration all voltage drops in the path of the charging current, for example, those associated with the power switch & boot-strap diode.
(c) the total impedance in the recharge current path, be sure to consider the hidden resistances such as those present within the +15V supply & its bypass capacitor, PCB tracks, the main power switch, and the boot-strap capacitor.

I would suggest a starting point would be to get some numbers for items 5 and 6. These numbers feed into the requirement for item 4, and if you then know items 4a and 4b this then allows you to calculate the maximum permitted value for item 4c.

If item 4c turns out to be an unachievably low resistance, say, 1 nano-ohm, then you will need to make some changes to the circuit, such as:
(a) increase the supply voltage that charges the boot-strap capacitor;
(b) reduce the voltage drops in the charge current path (eg: choose a boot-strap diode with a lower forward voltage drop);
(c) reduce the parasitic resistance in the components in the recharge path, eg: choose a boot-strap capacitor with a lower resistance;
(d) a combination of the above.

Once item 4 is determined and meets the requirements, then you can proceed to consider items 3, then 2, then 1 (in that order) to select the boot-strap capacitor.

  • 1
    \$\begingroup\$ Although this discussion is a few years old, I think it is worthwhile to revisit and perhaps create a schematic that illustrates the issue with bootstrap circuits in general, and maybe show possible solutions. But I doubt there will be any clever and practical way to improve upon the time-proven simple separate isolated gate drive power supplies that can be implemented with a square wave oscillator and a small transformer with perhaps three isolated windings, diodes, and capacitors. And of course the purpose-built TLP350 or similar components are good choices. \$\endgroup\$
    – PStechPaul
    Sep 10 at 3:55
  • \$\begingroup\$ @PStechPaul Agreed, I am not sure why I responded to this old question, perhaps because it appeared in the "review queue" as being not closed off. Cheers. \$\endgroup\$ Sep 10 at 4:13
  • 1
    \$\begingroup\$ For what its worth even though this was what seems like an age ago, I appreciated reading it, and will try to keep it in mind of anything similar in the future. For applications like this where they are quite low duty cycle so the charge time isn't critical, is there a way to determine sensible maximum values for C, I note there is a Bootstrap Diode Current Limit in the datasheet, would this be something the user needs to keep current less than, or the chip internally limits to. \$\endgroup\$
    – Hugoagogo
    Sep 11 at 0:52

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge that you have read and understand our privacy policy and code of conduct.

Not the answer you're looking for? Browse other questions tagged or ask your own question.