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I am using Quartus 18.0 and have set the settings for VHDL-2008. However, when I try to compile a trivial project where one "external name" signal exists, I get this error:

Error (10500): VHDL syntax error at LED.vhd(16) near text "<"; expecting an identifier, or a string literal

This proves that "external name" which is declared using << and >> symbols, cannot be used in synthesizable code. I have confirmed that this fails in Microsemi Libero and also in Intel Quartus Prime Standard. My question is why?

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    \$\begingroup\$ See Doulos VHDL-2008 Ease of Use Hierarchical Names or VHDL 2008 Just the New Stuff 2.1 External names "VHDL-2008 provides a new naming feature, external names, that allows us to write a testbench that accesses items not normally visible according to the hierarchical scope and visibility rules." External names are provided for verification purposes. \$\endgroup\$
    – user8352
    Sep 18, 2019 at 10:23
  • \$\begingroup\$ The thing is, I might need to connect internal names to device pins for debug purpose and just synthesize it into the design itself. \$\endgroup\$
    – gyuunyuu
    Sep 18, 2019 at 10:46
  • \$\begingroup\$ That sounds like an XY problem where you're asking about your intended solution instead of how to solve the underlying problem. \$\endgroup\$
    – user8352
    Sep 18, 2019 at 11:16

2 Answers 2

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Because hierarchical names do not use ports. You can refer to a signal in a different level/module, bypassing all I/O ports.

To physical get to the signal the synthesis tool would have to auto generate additional I/O ports. It might be possible to implement this but I suspect that would open a whole can of worms.

I maybe very old fashioned because I would not like a design to start routing signals between modules and hierarchies without me having very tight control over them.

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  • \$\begingroup\$ There's no technical reason that the tool couldn't add the connections specified by external names as it flattens the hierarchy to create the final netlist. But I suspect that synthesis tool vendors wisely disallow it because it would make supporting their customers a nightmare. But most vendors offer an embedded logic analyzer tool for debugging (Intel SignalTap, Xilinx ChipScope, etc.) that DOES allow arbitrary connections throughout the design hierarchy. \$\endgroup\$
    – Dave Tweed
    Sep 18, 2019 at 11:30
  • \$\begingroup\$ SignalTap, ChipScope, etc. don't insure timing. Global signals declared in packages aren't generally supported for synthesis either. \$\endgroup\$
    – user8352
    Sep 21, 2019 at 10:05
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This structure is only supported in VHDL 2008 release. Be sure you have the correct switch set that is not always the case by default inside IDE tools. Your problem seems more to be a syntax error than a synthesis one.
Another workaround is to use some pragmas keywords inside your code to skip the inside excerpt not be analyzed by the synthesizer.

-- synthesis_off
-- not synthesize-able code here!
-- synthesis_on
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  • \$\begingroup\$ I have concluded that the feature is only intended for simulation and not ever for synthesis. Therefore, synthesis tools do not support. \$\endgroup\$
    – gyuunyuu
    Mar 23, 2021 at 23:38

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