I am using Quartus 18.0 and have set the settings for VHDL-2008. However, when I try to compile a trivial project where one "external name" signal exists, I get this error:
Error (10500): VHDL syntax error at LED.vhd(16) near text "<"; expecting an identifier, or a string literal
This proves that "external name" which is declared using << and >> symbols, cannot be used in synthesizable code. I have confirmed that this fails in Microsemi Libero and also in Intel Quartus Prime Standard. My question is why?
VHDL-2008 Ease of Use
Hierarchical Names orVHDL 2008 Just the New Stuff
2.1 External names "VHDL-2008 provides a new naming feature, external names, that allows us to write a testbench that accesses items not normally visible according to the hierarchical scope and visibility rules." External names are provided for verification purposes. \$\endgroup\$