enter image description here

Here is MISO in yellow and MOSI in purple. I thought I would use a ferrite bead in series of each signal to filter out the noise.

I will be making hundreds of these boards. I'm not sure it is worth fixing, but I wanted these boards to be reliable as possible.

Here is an updated photo: 1. yellow CS 2. light blue sclk 3. purple MISO 4. dark blue MOSI I used 4 probes on 10x with close grounds. I am running SPI at 2Mhz. The under and overshoot (see ringing) on MISO is 1V magnitude. It seems the ringing couples to MOSI. How can I mitigate this? Would a series 33ohm resistor help? enter image description here

  • 1
    \$\begingroup\$ can we see the clock as well? \$\endgroup\$
    – D Duck
    Commented Sep 19, 2019 at 20:26
  • 6
    \$\begingroup\$ How are you probing the line? How big is the ground loop on your lead? \$\endgroup\$
    – BB ON
    Commented Sep 19, 2019 at 20:31
  • 2
    \$\begingroup\$ Actually, @BBON has a good point. Your ground might be really far away from your probe and you could be accidentally making a giant antenna. Also, this seems to be okay but you need to clarify why you believe this is an issue. Is it causing incorrect information across your SPI bus? \$\endgroup\$
    – user103380
    Commented Sep 19, 2019 at 20:32
  • \$\begingroup\$ What @BBON said is helpful, ground was far away, although I also measured with ground close, but not this photo. \$\endgroup\$
    – Bill
    Commented Sep 19, 2019 at 20:47
  • 1
    \$\begingroup\$ @BSEE Can we see the relevant part of your PCB layout? \$\endgroup\$ Commented Sep 24, 2019 at 3:31

2 Answers 2


There are two potential issues that come to mind:

  1. Signal integrity affecting reliability of communication.

Although you don't say so explicitly, I'm assuming you don't see any indication of corrupted data in either direction. But that's not enough - you want to know how much margin you have, both in time and in voltage, to datasheet guaranteed thresholds. If those margins are very healthy (exactly what that means is an engineering judgement call) then you have some confidence that things will still be ok on different units and at different temperatures and over modest variations in supply voltage etc.

If the margins are not enormous then you can gain some confidence (or concern) by testing on different units and at extremes of anticipated temperature and supply voltage. Don't just functionally test - take scope measurements in all of those conditions and see how much the margins change.

SPI can generally tolerate quite substantial ringing, overshoot, crosstalk and other waveform ugliness on the MOSI and MISO signals - more extreme than I see in the scope shot provided - provided they are adequately settled by the time the sampling edge on SCLK occurs. Integrity of SCLK and to a lesser extent CS is more critical, because there is logic in the slave and/or master that's triggered by the edges of those signals. Monotonicity of SCLK is particularly important. You haven't provided scope shots of SCLK so I can't comment on how yours looks. As BBON notes, correct probing technique is important to prevent things from looking worse than they actually are. Conversely, sometimes probe tip capacitance will slow down an overly rapid edge, mitigating ringing and overshoot and giving false confidence. At least make sure you're using a 10x probe rather than 1x to reduce the loading effects.

  1. Overshoot and undershoot violating abs max voltage ratings.

The signals appear to briefly exceed 3.3V on the rising edge and go below 0V on the falling edge. If severe enough, this can cause cumulative damage to the receiving buffer structure in the ICs.

Typically they can tolerate up to 0.3 V above Vdd and 0.3 V below GND indefinitely without any problems, but check the datasheets.

Usually they can tolerate larger excursions than that if they are very brief (as they will be in overshoot) without damage, even when repeated billions of times. However, often the datasheets do not give info on this, and if they don't and you care a lot about long-term reliability then you should ensure you don't exceed the DC absmax even for nanoseconds.

Termination of some kind will help with this. For digital signals up to tens of MHz, adding a 33 ohm resistor in series with each output driver (close to the driving IC) will usually tame it adequately without needing to bother with fancier term schemes or controlling the impedance of the PCB traces.

Also, apparent overshoot/undershoot is very often just due to inadequate probing technique, so make sure you're doing that right before wasting time with circuit mods.

  • 2
    \$\begingroup\$ I don't want to add another answer since yours is well-written, but there is one other option than termination: some MCUs and MPUs actually allow setting the drive strength (I know STM32F, STM32L and BCM283x do, presumably the STM32MP does too). Of course this leaves the issue of MISO but reducing drive strength might be a valid solution without adding new elements. \$\endgroup\$
    – jaskij
    Commented Sep 19, 2019 at 23:08
  • \$\begingroup\$ Why do you recommend 33Ω termination at the driver? Wouldn't it be better to use 50Ω microstrip with termination at the receiver? \$\endgroup\$ Commented Sep 19, 2019 at 23:30
  • \$\begingroup\$ @CalebReister usually the output driver itself has an effective impedance somewhere in the neighborhood of 15-25 ohms which is additive to the external series src term. Actual legit 50 ohm microstrip is overkill and wastes board area and $$ in verification testing during fabrication. Shunt terminating at the receiver increases power consumption and likely exceeds the max allowable output current of typical CMOS drivers and will reduce the voltage swing, usually violating the receiver's Vih/Vil. \$\endgroup\$ Commented Sep 20, 2019 at 0:07
  • \$\begingroup\$ With your sample spacing of 4 nanoseconds, you probably are not seeing the full-amplitude overshoots. I used a 900MHz FET probe on outputs of a XILINX FPGA, decades ago, with 1nanosecond edges; the 1pF FET probe (using 10:1 divider) showed both overshoot by 5 volts and undershoot by 5 volts. Yes, the ESD diodes were turning on, injecting lotta substrate currents, and royally trashing the silicon operations. I suggest you insert 75 ohm or 100 ohm in series, at the driving end of those traces (at the source). \$\endgroup\$ Commented Sep 20, 2019 at 4:33
  • \$\begingroup\$ I like the wisdom of these posts and see I can more effective of my probing. I can redo this test with the techniques mentioned. My scope is 100Mhz Rigol with 150Mhz passive probes. I will do this Monday and post an image. \$\endgroup\$
    – Bill
    Commented Sep 20, 2019 at 23:29

So your signal has an underdamped response, which in most cases is fine, but your overshoot is a little too high. You are getting a second-order response from the system.

Step Input

\$X(s) = \cfrac{1}{s}\$

Second-Order Transfer Function

\$H(s) = \cfrac{A\omega_n^2}{s^2+2\zeta\omega_n+\omega_n^2}\$

So since it is underdamped you need to increase your \$\zeta\$ parameter as of right now, it is less than one.

The easiest way you can increase your dampening is to add more resistance someplace in your circuit. Having some overshoot decreases your settling time, as opposed to having it critically damped or overdamped.

Without knowing your exact setup, I cannot tell where to put the resistive element, but if you add inductance, the overshoot will likely get worse.

As for reliability, I doubt it would affect your ability to reliably transmit data, but you can fix it fairly easily by tweaking some passive circuit-element values.


Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.