enter image description here

The pullups on my i2c lines are 4.7k. People are afraid of draining the battery by fixing this waveform with smaller pullups, like 2.2k. It doesn't seem much power is wasted considering the short duration of the bus being low (2-4 byte transfers) and the 400k bus speed. I am concerned about reliability with the waveform this distorted. What is the effect of the curving leading edge? It would seem to delay sampling of sda on the rising edge of scl.

  • 2
    \$\begingroup\$ What devices these are? As long as all devices see bus states and timings correcrly based on their input high voltage and input low voltage tresholds, then it should work. You can slow down the speed if necessary to get high, low, rise and fall times within margins if they are not. \$\endgroup\$ – Justme Sep 19 '19 at 20:51
  • \$\begingroup\$ "2-4 byte transfers" doesn't say anything unless you also know the number of transfers per second. \$\endgroup\$ – pipe Sep 19 '19 at 21:02
  • \$\begingroup\$ If you can alter the data stream: smaller resistors + shorter or less frequent data = about the same current. \$\endgroup\$ – rdtsc Sep 19 '19 at 21:06
  • \$\begingroup\$ Welcome to EE.SE! Keep in mind that questions about optimization (i.e., "What is the best ...?") require a definition about what problem dimensions are to be optimized for your application, such as size, speed, energy consumption, user experience, etc. Since these can't be optimized all at once, you need to have a good idea of which ones are most important to you, and be able to articulate that clearly to us. \$\endgroup\$ – Dave Tweed Sep 19 '19 at 21:12

Short answer: You are absolutely right not to worry about the smaller pullup resistors, since your bus will be in a high state the vast majority of the time. Moreover, the slow rise times will probably increase the power consumption significantly. Just use the 2.4kΩ resistors.

Long Answer

Very slow edge rates will actually cause CMOS inputs to consume more power than faster edge rates. Let's take a look at a typical CMOS input stage:

CMOS input stage. Source: Texas Instruments

When the input voltage is in an intermediate state, both the PMOS and NMOS transistors will be partially on, resulting in a surge current (typically on the order of several milliamps). This current will be drawn by every device on the bus as long as the voltage is in an intermediate state.

It is reasonable to assume that most I2C devices use Schmitt trigger inputs, which are designed to handle slow input transitions. However, do Schmitt trigger inputs consume less power? Unfortunately, no. This is a common misconception, so let's look at a typical CMOS Schmitt trigger:

CMOS Schmitt trigger input stage. Source: Texas Instruments

Note that the basic structure stays the same, meaning that surge current is still a problem.

So, long story short: the slow rise times from the weak pullup resistors will most likely increase power consumption. This is especially true if there are multiple devices on the bus.

Take a look at these articles from Texas Instruments for more information:

| improve this answer | |
  • \$\begingroup\$ Great answer that gets right to the most important point and explains it clearly. \$\endgroup\$ – pericynthion Sep 19 '19 at 22:44

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.