The pullups on my i2c lines are 4.7k. People are afraid of draining the battery by fixing this waveform with smaller pullups, like 2.2k. It doesn't seem much power is wasted considering the short duration of the bus being low (2-4 byte transfers) and the 400k bus speed. I am concerned about reliability with the waveform this distorted. What is the effect of the curving leading edge? It would seem to delay sampling of sda on the rising edge of scl.
Short answer: You are absolutely right not to worry about the smaller pullup resistors, since your bus will be in a high state the vast majority of the time. Moreover, the slow rise times will probably increase the power consumption significantly. Just use the 2.4kΩ resistors.
Very slow edge rates will actually cause CMOS inputs to consume more power than faster edge rates. Let's take a look at a typical CMOS input stage:
When the input voltage is in an intermediate state, both the PMOS and NMOS transistors will be partially on, resulting in a surge current (typically on the order of several milliamps). This current will be drawn by every device on the bus as long as the voltage is in an intermediate state.
It is reasonable to assume that most I2C devices use Schmitt trigger inputs, which are designed to handle slow input transitions. However, do Schmitt trigger inputs consume less power? Unfortunately, no. This is a common misconception, so let's look at a typical CMOS Schmitt trigger:
Note that the basic structure stays the same, meaning that surge current is still a problem.
So, long story short: the slow rise times from the weak pullup resistors will most likely increase power consumption. This is especially true if there are multiple devices on the bus.
Take a look at these articles from Texas Instruments for more information:
- Implications of Slow or Floating CMOS Inputs (source for first image)
- Solving CMOS Transition Rate Issues Using Schmitt Triggers (source for second image)
- Understanding Schmitt Triggers