Since the end of 90s, it is known that side-channels (e.g. execution time, power consumption, electromagnetic emanations) of computation platforms can be analysed to recover information on data being manipulated (e.g. keys in cryptographic calculations).

On load/store architectures, it seems that the amount of leakage depends on the type of instruction. For instance, some papers report successful results when exploiting leakages related to intermediate values manipulated by memory instructions (e.g. load/store instructions) while ALU operations do not seem to produce any exploitable leakage. See for instance this paper for experimentations on ATmega2561 processor (using power consumption as side-channel) and this paper for experimentations on ARM-Cortex M3 processor (using electromagnetic emanations as side-channel).

How could we explain, from an architectural point of view, that ALU instructions might be less prone to information leakage than memory instructions?


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I think it should be obvious that anything that causes operations on memory is going to involve a lot more logic switching than operations that are handled entirely within the CPU itself. The signals associated with doing an "add" versus an "and" are going to be extremely subtle compared to everything else that is going on associated with instruction fetching and execution in general.


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