I would like to write the following in SVA (SystemVerilog Assertion) format.
signal a should never be 2 until it attains the value 1
How can we do that?
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4\$\begingroup\$ Sorry, I cant help it, this triggers immediately: "Four shalt thou not count, neither count thou two, excepting that thou then proceed to three." \$\endgroup\$– OldfartSep 22, 2019 at 7:42
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1\$\begingroup\$ ... Five is right out! \$\endgroup\$– Dave TweedSep 22, 2019 at 13:16
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1\$\begingroup\$ For the clueless: montypython.net/scripts/HG-handgrenade.php \$\endgroup\$– dave_59Sep 25, 2019 at 10:37
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2 Answers
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property p;
@(posedge clk) (A != 2) until (A == 1);
endproperty
assert property (p);
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\$\begingroup\$ Another related question: I want to generate the counter-example for this property. When I try
assert property (not(p))for that purpose, it says syntax error. Is there an issue with usingnotwithuntil? \$\endgroup\$ Sep 25, 2019 at 14:04 -
\$\begingroup\$ Another doubt: How can I write the following in SVA?
not(a until b)without usinguntilors_until. \$\endgroup\$ Sep 25, 2019 at 15:14 -
1\$\begingroup\$ You cannot use parenthesis
()with property expressions. \$\endgroup\$– dave_59Sep 25, 2019 at 16:56 -
\$\begingroup\$ Okay. What would be the recommended way if we want to negate such a property? The objective here is to get the counterexample corresponding to the property (hence the negation). \$\endgroup\$ Sep 26, 2019 at 6:43
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Such a condition requires a state machine, and cannot be done with simple assertions alone. You need to build the state machine, and then make an assertion that certain transitions cannot occur within that state machine.
answered Sep 22, 2019 at 13:18
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\$\begingroup\$ Do you mean state machine in the Verilog design or state machine in the SVA property (is that possible)? \$\endgroup\$ Sep 23, 2019 at 6:13
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