I would like to write the following in SVA (SystemVerilog Assertion) format.
signal a should never be 2 until it attains the value 1
How can we do that?
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Sign up to join this communityI would like to write the following in SVA (SystemVerilog Assertion) format.
signal a should never be 2 until it attains the value 1
How can we do that?
property p;
@(posedge clk) (A != 2) until (A == 1);
endproperty
assert property (p);
assert property (not(p))
for that purpose, it says syntax error. Is there an issue with using not
with until
?
\$\endgroup\$
Sep 25, 2019 at 14:04
not(a until b)
without using until
or s_until
.
\$\endgroup\$
Sep 25, 2019 at 15:14
()
with property expressions.
\$\endgroup\$
Such a condition requires a state machine, and cannot be done with simple assertions alone. You need to build the state machine, and then make an assertion that certain transitions cannot occur within that state machine.