# How to write 'a signal should never have certain value before it attains some other value' in SystemVerilog assertion?

I would like to write the following in SVA (SystemVerilog Assertion) format.

signal a should never be 2 until it attains the value 1

How can we do that?

• Sorry, I cant help it, this triggers immediately: "Four shalt thou not count, neither count thou two, excepting that thou then proceed to three." – Oldfart Sep 22 '19 at 7:42
• ... Five is right out! – Dave Tweed Sep 22 '19 at 13:16
• For the clueless: montypython.net/scripts/HG-handgrenade.php – dave_59 Sep 25 '19 at 10:37

Such a condition requires a state machine, and cannot be done with simple assertions alone. You need to build the state machine, and then make an assertion that certain transitions cannot occur within that state machine.

• Do you mean state machine in the Verilog design or state machine in the SVA property (is that possible)? – vineeshvs Sep 23 '19 at 6:13
• I just showed a very simple assertion. – dave_59 Sep 25 '19 at 9:30
property p;
@(posedge clk) (A != 2) until (A == 1);
endproperty

assert property (p);

• Another related question: I want to generate the counter-example for this property. When I try assert property (not(p)) for that purpose, it says syntax error. Is there an issue with using not with until? – vineeshvs Sep 25 '19 at 14:04
• Another doubt: How can I write the following in SVA? not(a until b) without using until or s_until. – vineeshvs Sep 25 '19 at 15:14
• You cannot use parenthesis () with property expressions. – dave_59 Sep 25 '19 at 16:56
• Okay. What would be the recommended way if we want to negate such a property? The objective here is to get the counterexample corresponding to the property (hence the negation). – vineeshvs Sep 26 '19 at 6:43
• Assert property ( not p) – dave_59 Sep 26 '19 at 6:45