0
\$\begingroup\$

I just don't think the word "near" is specific enough. Am I missing something before or after the word "else"? I'll put the code below and the errors after it. Thanks in advance!

library ieee;
use ieee.std_logic_1164;
use ieee.std_logic_arith;
use ieee.std_logic_unsigned;

entity decoBCDto7 is
    port(
            binary:     in std_logic_vector(3 downto 0);
            EN:         in std_logic;
            display:    out std_logic_vector(6 downto 0));
end decoBCDto7;

architecture internal of decoBCDto7 is
begin
    process(binary,EN,display)
    begin
        if(EN = '1') then
        with binary select
        display <=      "0111111" when "0000",
                        "0000110" when "0001",
                        "1011011" when "0010",
                        "1001111" when "0011",
                        "1100110" when "0100",
                        "1101101" when "0101",
                        "1111101" when "0110",
                        "0000111" when "0111",
                        "1111111" when "1000",
                        "1100111" when "1001",
                        "0000000" when OTHERS;      
        else
            display <= "0000000";

        end if;
    end process;
end internal;

Error (10500): VHDL syntax error at decoBCDto7.vhd(19) near text "if"; expecting "end", or "(", or an identifier ("if" is a reserved keyword), or a concurrent statement

Error (10500): VHDL syntax error at decoBCDto7.vhd(19) near text "then"; expecting "<="

Error (10500): VHDL syntax error at decoBCDto7.vhd(32) near text "else"; expecting "end", or "(", or an identifier ("else" is a reserved keyword), or a concurrent statement

Error (10500): VHDL syntax error at decoBCDto7.vhd(35) near text "if"; expecting ";", or an identifier ("if" is a reserved keyword), or "architecture"

\$\endgroup\$
  • \$\begingroup\$ I know nothing about VHDL but I would expect an end select before the else statement. \$\endgroup\$ – Transistor Sep 22 '19 at 21:26
1
\$\begingroup\$

Prior to VHDL-2008, a WITH-SELECT was a concurrent construct, not a sequential one. So you could't put a WITH-SELECT clause inside a sequential process.

Use a CASE statement instead. That will clear all the error messages and is supported across all releases of the VHDL standard.

| improve this answer | |
\$\endgroup\$
  • \$\begingroup\$ IEEE Std 1076-2008 provides support for sequential selected signal assignment. However the tool does not or does not support -2008. There's a missing suffix in the use clauses, e.g. use ieee.std_logic_1164.all making the elements of the package declarations visible (here std_logic_vector and std_logic). This will cause an additional error. The shown code also doesn't use declarations from packages std_logic_arith or std_logic_unsigned nor does the process sensitivity list need display which isn't evaluated (these are not errors). \$\endgroup\$ – user8352 Sep 22 '19 at 21:52
  • \$\begingroup\$ @user8352, I did check if it was a 2008 change but not deeply enough, evidently. Fixed. CASE is simpler as it works for all VHDL releases. \$\endgroup\$ – TonyM Sep 22 '19 at 22:04
  • 1
    \$\begingroup\$ The actual point of the comment was that That will clear all the error messages is not true due to the missing suffix for the use clause use ieee.std_logic_1164; There's no other declaration making std_logic_vector nor std_logic visible. \$\endgroup\$ – user8352 Sep 22 '19 at 22:43

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.