# PMOS Load Switch Circuit issue

I'm working on a load switch circuit that drives a capacitive load of 1000 uF and a GaN transistor in parallel. The schematic of the circuit is attached. The input voltage is 50 V and the PMOS being used is IRF5210. The simulations show promising results(also catering the inrush currrent issue), but on the hardware, when the GaN is biased to -2.9 V and the pulse is applied to the NPN transistor, the circuit turns on but draws the maximum current from the supply. Hence, the PMOS gets burned. The inrush current is limited to 0.4 A max and the full load current can go up to 7 A.

Any suggestions will be welcomed. Thankyou]1

(original)

I am trying to work on the overvoltage and undervoltage protection circuitry and if the supply voltage is within the 45 to 55 VDC range, then the voltage may be transferred onwards. For that purpose, I designed this load switch circuitry. The NPN transistor is MJE13003 that switches ON/OFF depending upon the comparator's output signal (Here assume simply there is a 5 V ON signal coming, so the NPN biases the PMOS (IRF5210) and hence turns it ON). For inrush current limitation, I used this 20 uF cap to limit it according to the application note. The GaN at the output is QPD1881L.

• What (on earth) is C2 for and why 20 uF? || Where is the GAN transistor - is that the 120 OhmS. || It is far from obvious how the diagram and the text relate. HOW are you expecting the inrush current not to be approximately infinite ? :-). 1000 uF with 50V dumped into it with no formal series load = !!!!!!!!!!!!!!. – Russell McMahon Sep 23 '19 at 10:34
• 1) C2 is the inrush limiter capacitor and its value is calculated using the on semiconductor application note onsemi.com/pub/Collateral/AND9093-D.PDF. 2) The Gan transistor is not shown in the figure as i couldnt simulate it in MUltisim. The 120 ohm load is the dummy load connected here – sam14 Sep 23 '19 at 11:02
• Plus the inrush current, as observed in the simulations, is almost around 600mA (max). You said it is expected to be infinite. Kindly elaborate otherwise and correct me if I'm wrong kindly. Thankyou. – sam14 Sep 23 '19 at 11:07
• Ah. Ok :-) - You are going to have to explain the circuit in 'slightly' more detail - ideally on the diagram. If no GAN use the closest symbol availabvle and label it. Where is the NPN transistor. What are the relevant timing and place in time when these things happen. What is the NP and GAN part number (and show on diagram). ||If I understand what you are doing you are charging the cap OK, and THEN some time afterwards applying a fast switched load (GAN + NPN) . The FET is by now hard on so it sees the GAN load which perhaps is close to a short?. ... – Russell McMahon Sep 23 '19 at 11:24
• PLEASE provide complete cct. Is there a 2nd NPN. Part numbers. All components and connections ... . – Russell McMahon Sep 23 '19 at 11:26