I'm working on a load switch circuit that drives a capacitive load of 1000 uF and a GaN transistor in parallel. The schematic of the circuit is attached. The input voltage is 50 V and the PMOS being used is IRF5210. The simulations show promising results(also catering the inrush currrent issue), but on the hardware, when the GaN is biased to -2.9 V and the pulse is applied to the NPN transistor, the circuit turns on but draws the maximum current from the supply. Hence, the PMOS gets burned. The inrush current is limited to 0.4 A max and the full load current can go up to 7 A.
Any suggestions will be welcomed. Thankyou]1
I am trying to work on the overvoltage and undervoltage protection circuitry and if the supply voltage is within the 45 to 55 VDC range, then the voltage may be transferred onwards. For that purpose, I designed this load switch circuitry. The NPN transistor is MJE13003 that switches ON/OFF depending upon the comparator's output signal (Here assume simply there is a 5 V ON signal coming, so the NPN biases the PMOS (IRF5210) and hence turns it ON). For inrush current limitation, I used this 20 uF cap to limit it according to the application note. The GaN at the output is QPD1881L.