2
\$\begingroup\$

Below the SOA for the IXFP6N120P:

enter image description here

And the SOA for the IRFBG30:

enter image description here

The first one shows a DC line beyond 100 ms, but the second one does not. Does this mean the second one is unreliable beyond 10 ms, or the manufacturer decided not to put a DC line assuming the area beyond 10 ms is safe?

\$\endgroup\$
1
\$\begingroup\$

If you notice, the IRFBG30 does not have a 100ms line either.

Generally speaking, the manufacturers do not put SOA lines that do not intersect the \$V_{DS(MAX)}\$ vertical line and from inspection it appears that would be the case for the 100ms line for the IRFBG30 (it looks as if it would terminate at about 500V).

The DC line would be similarly constrained at a much lower voltage.

An interesting thing about SOA graphs; they are showing that if you can somehow hold the case temperature at 25C then the lines shown will not result in excess dissipation (Tj at 150C in this particular case) but holding the case at 25C (unless you are outside in the Antarctic and even then it might be troublesome) is nigh on impossible.

This application note from Ixys is recommended reading.

\$\endgroup\$
1
\$\begingroup\$

The manufacturer will generally try to claim as much as they can. So if they don't put any claims in for pulses longer than 10mS, then you should wonder why, rather than trying to extrapolate for what they 'should' have put there.

Be warned that there is a thermal runaway mechanism in FETs for long pulses. The die is made up of many cells in parallel. Although the RDSon has a positive tempco, so that when switched hard on the die will share currently nicely, the Vth has a negative tempco, which means that when operating in the linear region (that is with a finite current and a voltage well above 0v), there is a thermal instability in how the die share current. For short pulses, there is not the time for them to 'unshare' current, for long pulses they can run away with just a few die hogging all the current and burning out.

So with no claims for operation longer than 10mS, and a mechanism for why you should avoid long pulses, I'd respect the published SOA if I were you.

\$\endgroup\$
0
\$\begingroup\$

In my experience, high-current die are thinned from 300 micron down to 100 micron. What does that tell us, in the absence of die-substrate doping info? not much.

But the thermal behavior is still available, if we perform a tiny bit of physics.

The thermal time constant of a cubic meter of silicon, with heat entering one face and exiting the opposite face and the other 4 sides being thermally insulated, is 11,400 seconds.

What about 100 micron cube?

The thermal time constant of 0.1 meter cube is 100X faster, at 11,400/100 = 114 seconds. Sketch a cube, slice it into 1/10th cubes in all 3 dimensions, and you'll observe that 100X speedup; volume is down 1,000X, but heat path resistance is up 10X, hence the 100X smaller thermal time constant.

The thermal time constant of 0.01 meter cube is 100X faster, at 1.14 seconds.

The thermal time constant of 0.001 meter cube is 100X faster, at 0.0114 seconds.

And the thermal time constantof 0.0001 meter (100 micron) cube is still another 100X faster, at 0.000114 seconds (or 114 microSeconds).

Thus in 100 micron-thick PowerMOSFET structures, these long pulses are no longer thermally-absorbed within the die, and the die (and the metal mounting plate) begins to heat up and allow all the various temperature effects, mentioned by Neil_UK and by Peter Smith, to cause problems.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.