Is it permissible to use a condition generated by one clock with another, fully-synchronized clock (generated by a PLL with 0 phase shift) of different frequency?
This works as expected in simulation:
`default_nettype none `timescale 1ns/1ps module top; reg base_clk = 0; reg fst_clk = 0; reg cond = 1'b0; reg [2:0] ctr = 3'd0; reg some_reg = 1'b0; always #15 base_clk = !base_clk; always #5 fst_clk = !fst_clk; initial begin $dumpfile("top.vcd"); $dumpvars(0, top); #10000 $finish; end always @(posedge base_clk) begin ctr <= ctr + 1'b1; if (ctr == 3'd5) cond <= 1'b1; else cond <= 1'b0; end always @(posedge fst_clk) begin if (cond) some_reg <= 1'b1; end endmodule
Can I assume this will also work when synthesized (in synthesis
fst_clk would be generated by a PLL)? In my mind there shouldn't be any issues here since the clocks are synchronized and so I'm not crossing clock domains. Am I correct in thinking this? Or, have I overlooked something and I should only use a condition generated by the same clock.