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schematic

simulate this circuit – Schematic created using CircuitLab

Considering Vdd=5v I want to calculate the node voltages at P,Q and R.

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  • \$\begingroup\$ You've entered your design into a simulator. Add a source and what does the simulator say? \$\endgroup\$ – The Photon Sep 25 at 17:32
  • \$\begingroup\$ Are you asking for the trivial solution, or is there more to the "circuit"? \$\endgroup\$ – W5VO Sep 25 at 17:45
  • \$\begingroup\$ I just want values. This is the circuit. \$\endgroup\$ – Rohan Gaonkar Sep 26 at 3:30
  • \$\begingroup\$ What i think is voltage at Q is Vdd-2Vtn. And voltage at P is Vdd-3Vtn. Is this correct? \$\endgroup\$ – Rohan Gaonkar Sep 26 at 3:32
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One side of this circuit is biased into saturation, and one side is in cutoff. the node voltages are a consequence of that. When Vdd is much greater than Vgs-Vtn and Vgs is much greater than Vtn, the transistor is in saturation. When Vdd is much less than Vgs-Vtn, the transistor is in cutoff. From that, you should be able to develop a sense of which ones are passing current and which ones are not.

Transistors going back and forth between saturation and cutoff without being used in the triode region may be thought of as switches. Their output voltage is either +(Vdd-Vtn) or 0 depending on their operating region.

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