RS485 Eye diagram - does it look good?

I got a new diff probe, I am trying it out on RS485. I'm triggering on the rising edge. The RS485 is running at 25Mhz.

Does the eye diagram look good?

Could I double the speed (50MHz) and be ok? (do I need to worry about overshoot?)

What should one look for in an eye diagram?

Probe is TEK TDP1000 (1GHz, 200MHz scope) cable length is 1m with 50MHz transcievers.

• Is it normal for the intersection to be so high? What differential probe did you get? I have two HVP70 arriving today at my house. Sep 25, 2019 at 18:47
• Fancy. Fancy. Makes the THDP0200 we have at work look cheap. Sep 25, 2019 at 18:56
• It's nice when the boss wants to use the budget when they don't want to lose it. (and I never said that) Sep 25, 2019 at 18:58
• Maybe this will help. onsemi.com/pub/Collateral/AND9075-D.PDF Sep 25, 2019 at 18:59
• This is a nit, because that eye diagram is good enough even if it's asynchronous. RS-485 is just an electrical spec. What's going over the wire? Sep 25, 2019 at 19:46

No problem going to 2f is = 50 Mbps.

The probability of error depends solely on the Voltage becoming the wrong polarity when the discriminator has computed the polarity for that bit..

What affects the SNR? , that determines the BER.

The slew rate indicates a variable amplitude and thus a variable SNR declining signal level, this also means a declining BER.

The 90% Vpp amplitude of data occurs when the rise time Tr reduces to Tr=0.35/f. ( by definition)

Since the bit interval, Tb= 2/f, thus Tr=0.7Tb

Assume from the trace , Tr= 7ns

• then ideal max bit rate “may be” 0.7/7ns =100Mb/s.

However additional margin loss results from pattern dependent Inter-Symbol-Interference, ISI perhaps from pattern dependency e.g. 011 or 0011 vs 0101 or group delay distortion or random jitter reduces the ideal margin of 100% down to some number like 30% that “may” correlate to some probability of error, or Bit Error Rate, BER = 1e-9. This depends on several other factors beyond the scope of this answer. .

The affect is not visible with a single trace capture, but is visible when displayed with trace memory overwrites. We know the correlation between Standard Deviation of Gaussian Noise vs number of bits so this jitter can be measured on time interval ,TI counters and/or Phase Margin Analyzers or BER Window Margin Analyzers.

Since the visible transition is skewed or asymmetric from ideal 50% to ~ 90% This amounts to 40% of Tr and thus degrades the Phase Margin by 40% of 7 ns or +/- 2.8ns

• Is this question a good question? Sep 25, 2019 at 20:04
• Not really. A better question has measurable parameters and Design Goals or specs. with uncertainty how to apply them based on limited experience. This question suggests good image trace skills but nothing more. Sep 25, 2019 at 20:09
• One spec that I have is 50MHz (implied in the OP), what would you do to improve the question? Sep 25, 2019 at 20:10
• Show method of Clk data recovery, cause of Skew, measurements of skew , rise time, jitter with random data p-p over some long time interval.... at least show some understanding of bit error rate and optimization questions with lab tests etc etc and Show length of application vs measurement and compute MHz-m product the preferred limitation of RS485 Sep 25, 2019 at 21:20
• Always show assumptions and test measurements. Like cable type , length, discriminator, probe BW. Sep 25, 2019 at 21:27