I am breaking into the world of FPGA development at my internship for an aerospace company. I keep coming across the term "Dual-Purpose Pin" in the documentation for the Max 10 family of FPGA devices. I cannot figure out what this means, since these pins seem to each have one purpose (like DEV_OE, for example) yet they are referred to as Dual-Purpose. Can someone explain this to me?
These pins can be used for a specific purpose or used as general userI/O pin, this is the reason why they are called "Dual-Purpose Pin". Take DEV_OE for example. If you enable "device-wide output enable" function in Quartus, this pin is used to set all outputs tri-stated or not. If you disable this function in Quartus, this pin is available as a normal use I/O.