# Why DDRx I/O bus frequency is half effective frequency?

I've already known that I/O buffer transfers data on both the rising and falling edges of the clock signal.

But it really confused me why I/O bus frequency is half of effective frequency.

For example, in DDR2-800.

Basic memory clock is 200 MHz.

Use 4n-prefetch technology.

So the effective frequency equals 200MHz*4 = 800MHz from the processor (CPU)'s perspective.

Here's the point.

Since I/O buffer transfers data 800M times per second on both rising and falling edge, we can infer that, each time when it works, I/O buffer transfers 400M times on one single edge.

Thus the work frequency = 400 M times / 0.5 second = 800 MHz.

By this equation, I/O bus frequency should be equal to effective frequency, both 800 MHz.

But on Wiki page DDR its said to be 400 MHz. How to explain this?

• I think you mean "effective frequency" rather than "efficient frequency." – JRE Sep 26 at 10:58
• Why times 4? If state changes occur on both rising and falling edge you have 2 state changes per period. So 200 MHz * 2 = 400 MHz – Swedgin Sep 26 at 10:59

The 4N pre-fetch architecture means that 4 data words are pre-fecthed prior to the read burst from 4 different adjacent columns. This diagram assumes the row address hs already been latched by an activate command. In the actual data transfer burst, you can see DO n in the first transfer and from the datasheet