I try to determine which of two asynchronous pulses came first (after a synchronous reset) using an FPGA. The pulses are asynchronous because they are generated from ring oscillators (running on the FPGA and not synchronized with the system clock).
I want to use as few resources as possible. Should I use a latch or some flip-flops like below?
I am looking for a solution where the output stay stable even if subsequent pulses are generated.