0
\$\begingroup\$

I try to determine which of two asynchronous pulses came first (after a synchronous reset) using an FPGA. The pulses are asynchronous because they are generated from ring oscillators (running on the FPGA and not synchronized with the system clock).

I want to use as few resources as possible. Should I use a latch or some flip-flops like below?

schematic source

I am looking for a solution where the output stay stable even if subsequent pulses are generated.

\$\endgroup\$
  • \$\begingroup\$ Do you have a clock that runs at least at twice the frequency of the fastest of both ring oscillators? \$\endgroup\$ – DonFusili Sep 26 '19 at 11:44
  • \$\begingroup\$ Not at all. The ring oscillators oscillates at ~5-10x the speed of the system clock. \$\endgroup\$ – DurandA Sep 26 '19 at 11:53
  • \$\begingroup\$ What you have drawn above will not work. The best I can think off is the old fashioned two-nand-gates-with-feedback Flip-Flop. \$\endgroup\$ – Oldfart Sep 26 '19 at 11:59
  • \$\begingroup\$ Define "first" -- first after what event? \$\endgroup\$ – Dave Tweed Sep 26 '19 at 12:08
  • \$\begingroup\$ After a synchronous reset. \$\endgroup\$ – DurandA Sep 26 '19 at 12:25
1
\$\begingroup\$

You need to use the transition of clocks to lock other out from changing.

schematic

simulate this circuit – Schematic created using CircuitLab

Either locks out the other, unless both occur at the same time, where both latch with L_R_SELECT having precedence.

Reset clears flip-flops to start sequence.

\$\endgroup\$
  • \$\begingroup\$ Why are the bars of the "Q bar"/"Q not" (Q near RESET) from the flip-flops not visible in the schematic? \$\endgroup\$ – DurandA Nov 22 '19 at 15:27
  • \$\begingroup\$ If you edit the image they are there. Just resolution of the custom part. \$\endgroup\$ – StainlessSteelRat Nov 22 '19 at 18:29
0
\$\begingroup\$

Just a quick draft, I'm not sure if my idea would work or not:

enter image description here

explanation: at first, you reset the two flips flops: hence Q1 = Q2 = 0.

Pulse 1 is applied to clk1 and pulse 2 is applied to clk2.

We have D1 = 1 xor Q2 = 1 xor 0 = 1, same for D2 = 1. When the first pulse occurs, let's say pulse 1, Q1 will be set to D1 = 1 and hence the LED 1 will turn on.

Then the second pulse will occur, but now at D2 we will have 1 xor 1 = 0 so Q2 will remain at 0 and LED 2 will remain turned off.

So the only LED that will be ON indicates which pulse occurred first.

And this state will remain stable, even if subsequent pulses occur.

But you have to be sure that the propagation delays of your gates are lower than the period of your oscillators.

\$\endgroup\$
  • \$\begingroup\$ Why has it been downvoted? \$\endgroup\$ – Wheatley Sep 26 '19 at 14:36
  • 2
    \$\begingroup\$ You could also hook each D to the other not-Q. That way the first clk would reset not-Q, and subsequent clocks would have no effect until the next reset. The XOR gates above are essentially inverters. \$\endgroup\$ – Cristobol Polychronopolis Sep 26 '19 at 14:40
  • \$\begingroup\$ @CristobolPolychronopolis yes you are right, I haven't noticed. We could spare two xor gates. \$\endgroup\$ – Wheatley Sep 26 '19 at 14:44
  • 2
    \$\begingroup\$ I'm the downvoter, this won't work, the clocks are completely independent, so there is no lower bound on the required propagation delay that would ensure no race conditions/metastability will occur. So it's a bad answer. \$\endgroup\$ – DonFusili Sep 26 '19 at 14:48
  • \$\begingroup\$ @DonFusili OK I understand, thank you. \$\endgroup\$ – Wheatley Sep 26 '19 at 14:52

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.