I am trying to figure out the output of flop DFF_2 when

  1. If DFF_1 has hold violation. My answer - DFF_2(Q) = X

  2. If DFF_2 has hold violation. My answer - DFF_2(Q) = X

I understand the FF's go to meta-stable when there is a hold violation causing the simulator to assume a value of 'x' on the output 'Q'. Which brings me to my answers of DFF_2(Q) being x for both cases. Assuming i am clocking out data as in the normal operations. Is there any different behavior that i should know in this setup ? or Are my assumptions wrong ?


simulate this circuit – Schematic created using CircuitLab

  • \$\begingroup\$ Are we talking before or after the data is clocked? \$\endgroup\$ – Voltage Spike Sep 26 '19 at 21:03
  • \$\begingroup\$ before the data is clocked in. I am interested in value of DFF_2(Q) while we supply 4 clock cycles. \$\endgroup\$ – sxa144 Sep 27 '19 at 14:57

If DFF_1 experiences a hold-time violation then the output of DFF_1 will be unknown for that clock cycle. The Q output from DFF_1 may resolve to a valid 1 or 0 but we can't determine precisely the minimum time required for that to happen. So, at the next clock edge the output of DFF_2 would become unknown. Note that if the input to DFF_1 does satisfy its setup and hold requirements at the next clock edge, then the output of DFF_1 would have a known value at the same time that DFF_2 would have an unknown value.


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