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I recently came across a Xilinx SOC design in which the system clock which is configurable up to sub GHz, being an LVDS clock the output is been divided using a 1.2V rail, as shown below.

Will this bring more integrity in the clock, or improve the noise figures, or improve the slew rate?

The same is not observed in the design in case of clocks used for much higher frequency demands.

The part used for clock generation(U42) is a SI570, which is a popular low ppm, high quality clock source for FPGAs.

enter image description here

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Those resistors are simply biasing the receiver correctly to a common-mode DC voltage of 0.6V. There isn't enough context to determine why this is necessary; my guess would be that they're connected to an I/O bank that is using the 1.2V supply as Vcc, and the receivers need to be biased to 1/2 Vcc.

The resistors have little effect on the signal voltage, and they're not terminators, either.

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    \$\begingroup\$ yes i understood, but why lvds lines which are already efficient at Vcm 1.2 are brought much down to 0.6 \$\endgroup\$ – kakeh Sep 27 '19 at 11:48
  • \$\begingroup\$ I can't recall the name, but isn't there a different bus topology that has a 1/2 DC midpoint? The name is different from lvds if I recall. It's been a long time since I've used fpgas though. \$\endgroup\$ – MadHatter Sep 27 '19 at 12:10

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