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I'd like to use the PWM I/O on the SAMA5D2 Series Microprocessor (Microchip).What I'm confused about is why each PWM channel has a high and low output pin. The datasheet specifies

Each channel controls two complementary square output waveforms.

My understanding is that you only need one of these outputs to drive an external peripheral such as a fan. In what instance would two complementary PWM outputs be used? Also, do I need these two complementary waveforms to drive a 4-wire PWM fan?

I've added a I/O description and timing diagram example from the datasheet for clarity.

PWM I/O description

Timing Diagram Example

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    \$\begingroup\$ Many SMPS topologies require complementary gate drive signals. Synchronous buck, push-pull, half bridge, etc. \$\endgroup\$ – John D Sep 27 '19 at 15:58
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    \$\begingroup\$ I went ahead and merged the two questions, with this one as the master. This one asked the same question better. \$\endgroup\$ – W5VO Sep 27 '19 at 16:56
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Imagine you drive something in a PUSH-PULL configuration; then, PWMH can drive the high-side switch, whereas PWML drives the low side switch. Many of these PWM controllers even have a dead-time functionality to guarantee that both switches aren't on simultaneously

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  • \$\begingroup\$ What is the purpose of putting in dead-times in the PWM signal? \$\endgroup\$ – Abdel Aleem Jan 28 '19 at 14:23
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    \$\begingroup\$ as I said in my last sentence. \$\endgroup\$ – Marcus Müller Jan 28 '19 at 14:24
  • \$\begingroup\$ Could you put it in a more general context? \$\endgroup\$ – Abdel Aleem Jan 28 '19 at 14:26
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    \$\begingroup\$ No, I can't. My sentence on push-pull is complete. You just have a look at any push-pull configuration and ask yourself what happens when that dead-time isn't there and both switches are on simultaneously. As I suggested in my answer. \$\endgroup\$ – Marcus Müller Jan 28 '19 at 14:29
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    \$\begingroup\$ Because components are non-ideal (and sometimes other reasons), for example by having capacitance, relying on stuff happening simultaneously is a very bad idea particularly if it involves shorting your power rails through semiconductor power electronics. You need to leave wiggle-room. \$\endgroup\$ – Dannie Sep 27 '19 at 14:41
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Complementary PWM signals can be useful in designing an inverter with full bridge configuration, where you need to drive two MOSFETs/switch complementary to each other. And dead time insertion comes handy to prevent these two complementary MOSFETS from being short during transition.

As you can see in the image, gate pulses to MOSFET1 and MOSFET3 should be complementary, similarly for MOSFET2 and MOSFET4.enter image description here

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Regarding having complimentary signals:

True complimentary signals are often used for common-mode noise suppression or for other reasons, as mentioned in the comments immediately below the question.

However, the diagram provided shows slight differences in timing, with the Low side versions starting later and completing sooner than the High side. As mentioned in another answer, hysteresis or avoidance of simultaneity may be part of the reasoning for the timing difference between the High and Low signals on the same channel. Also, the drawing implies quadrature, but that may just be for the example diagram.

I am not familiar with this device, nor with what the PWM interface was designed to work. Answers to those questions may help illuminate the reason for the extra lines, and (if you are lucky) might be discussed in the processor's data sheets or app notes.

Regarding a 4-wire PWM fan, I do not believe that both lines are necessary (at least for an inexpensive computer fan).

You may this link may be useful. https://www.ekwb.com/blog/what-is-pwm-and-how-does-it-work/ It provides information about the specifics of the wires and a reasonable bit of information regarding the use of PWM in an inexpensive 4-wire computer fan.

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