Like any FPGA vendor, Lattice provides a number of IP modules for users to put in their designs. I tend to use them whenever possible, but sometimes I doubt if they have any substantial benefit over plain Verilog.
For example, I can create a simple multiplier using the IPX dialog:
or do the same thing with a PMI intrinsic:
pmi_mult #( .pmi_dataa_width (9), .pmi_datab_width (9), .pmi_sign ("on"), .pmi_additional_pipeline (0), .pmi_input_reg ("off"), .pmi_output_reg ("off"), .pmi_family ("XO"), .pmi_implementation ("LUT")) ...
But given that I do not need additional pipeline stages or latching, is it any better than Verilog built-in multiplication operator? Like the following:
wire signed [8:0] a = (...); wire signed [8:0] b = (...); wire signed [17:0] result = a * b;
Shouldn't the LSE (or Synplify) be able to automatically match multiplication to
pmi_mult, addition to
pmi_add, and so on? Can I rely on it and just use plain Verilog arithmetic for simple computations?