I am using this 3.3V LDO whose input Vin=5V (regulated input.) Output is 3.3V with load current of 200mA
This 3.3V is given to this Microcontroller for GPIOs.
I have taken 2 outputs (these are sctive Low signals during normal operation and must be active high during sleep) from this 3.3V GPIO domain and connected to another IC with a +5V pullup. (Connected the +3.3V port to a +5V pull-up to meet the Vih/Vil levels of the connected IC and due to lack of +5V GPIO ports)
These two outputs are configured as open drain outputs (with no internal pull-up enabled inside the micro,) as we have pullups outside the micro, snd these are fed to the IC.
Micro is driving these two outputs as active high during sleep time.
During microcontroller sleep state, I am observing +4.2V at the 3.3V LDO output cap.
What might be the reason? Why am I getting +4.2V instead of +3.3V at the LDO output?
During normal operation, it works fine. I am getting only +3.3V at the LDO output. Main concern is only during the sleep state.
Does the internal clamping diode inside the micro do something (create a sneak path?) Can I infer something from the internal LDO Architecture?
I have attached a simple crude image of my problem. Please check.
What could be the reason and what could be a possible solution to overcome this?