I was reading in a book that it is often possible to realize a certain capacitance in Integrated Circuits by exploiting the Gate Capacitance of a MOSFET. I read that the main disadvantage of this technique is the presence of a resistance between drain and source, which determines some losses. The equivalent model of this structure is shown in the following picture:

enter image description here

Now my questions are:

1) The first plate of the capacitor is the Gate metal contact. Under it, there is the oxide. Under the oxide, the substrate. Which is the second plate?

2) Why are in this model S and D shortcircuited?

3) Why does the resistance between S and D become a series resistance?

  • \$\begingroup\$ for lowest resistance, the MOSFET should be biased ON, thus the Vgate should be above Vthreshold. \$\endgroup\$ – analogsystemsrf Sep 28 '19 at 12:45
  1. Obviously the other plate is S (which generally is connected to the substrate) and D (which is connected in this case also to S) and the channel inbetween.
  2. S and D both together and the channel form the second plate (you could also use only S but that would even increase the unwanted resistance)
  3. In the center picture the second plate is represented by the the line between both resistors. So the two restsors in the center picture are two series resitors connected in parallel. You can replace those two resistors by a single series resistor (right picture). See modified picture below: enter image description here

Note: If this derivation seems somewhat sloppy the sloppy part is not between 2nd (center) and 3rd (right) picture but between the 1st (left) and 2nd (center) picture.
Without mentioning there is a transition from an actually distributed element situation (the channel resistance is distributed over the whole plate which is part of a capacitor) to a lumped element representation.

  • \$\begingroup\$ Thank you for the answer. I do not understand physically the passage from picture 1 to picture 2. My doubt regards the resistance rds in picture 1. Is it in parallel with the plate? \$\endgroup\$ – Kinka-Byo Sep 28 '19 at 10:10
  • \$\begingroup\$ There are two resistors each connecting the terminal with the plate (one going via S and one going via D). Both resistors are in series concerning the terminal to plate connection (that's why I called them "series resistors"). But both of those series resistors are connected in parallel with each other (try to imagine them in the vertical part of the connection between terminal and plate). \$\endgroup\$ – Curd Sep 28 '19 at 10:16
  • \$\begingroup\$ Perfect, thank you! \$\endgroup\$ – Kinka-Byo Sep 28 '19 at 10:19
  • \$\begingroup\$ Concerning the situation in 1st (left) picture: the resistance is distributed over the whole plate. It is not in parallel with the plate; it is the plate. \$\endgroup\$ – Curd Sep 28 '19 at 10:19

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