I was reading in a book that it is often possible to realize a certain capacitance in Integrated Circuits by exploiting the Gate Capacitance of a MOSFET. I read that the main disadvantage of this technique is the presence of a resistance between drain and source, which determines some losses. The equivalent model of this structure is shown in the following picture:
Now my questions are:
1) The first plate of the capacitor is the Gate metal contact. Under it, there is the oxide. Under the oxide, the substrate. Which is the second plate?
2) Why are in this model S and D shortcircuited?
3) Why does the resistance between S and D become a series resistance?