I have a question about work-group scheduling on multiple CUs in Intel FPGA. As work-groups are assigned to available CUs, when is a CU considered available? Is it when the last work-item of the previous work-group has abandoned the pipeline or when it is at its second stage (so every stage of the pipeline is occupied by the previous work-group except the first one)? This decision is taken by the hardware scheduler, but I haven't found any public documentation explaining any of this.
Edit: I'm talking about the automatic process that takes place when using Intel OpenCL SDK for FPGA, not a custom design with HDL.