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I have a question about work-group scheduling on multiple CUs in Intel FPGA. As work-groups are assigned to available CUs, when is a CU considered available? Is it when the last work-item of the previous work-group has abandoned​ the pipeline or when it is at its second stage (so every stage of the pipeline is occupied by the previous work-group except the first one)? This decision is taken by the hardware scheduler, but I haven't found any public documentation explaining any of this.

Edit: I'm talking about the automatic process that takes place when using Intel OpenCL SDK for FPGA, not a custom design with HDL.

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  • \$\begingroup\$ Um, I'm no expert on this subject, but Intel is a manufacturer (probably the second largest) of FPGAs, and what you do with these, including what kind of pipelined processing you put on there, is not their business? \$\endgroup\$ Sep 29 '19 at 14:42
  • \$\begingroup\$ Of course. Maybe this needs clarification. I'm talking about the mapping produced by Intel OpenCL SDK for FPGA, not a custom one. \$\endgroup\$ Sep 29 '19 at 14:47
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    \$\begingroup\$ @HastatusXXI It sounds like what you're asking about is more specific to the OpenCL architecture, then, than to Intel FPGAs (damn, it still feels weird saying Intel there instead of Altera...) \$\endgroup\$
    – Hearth
    Sep 29 '19 at 15:07
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    \$\begingroup\$ @HastatusXXI You should mention this in the question. \$\endgroup\$ Sep 29 '19 at 15:17
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    \$\begingroup\$ Edit your question to add detail, don't leave it in comments. \$\endgroup\$
    – TonyM
    Sep 29 '19 at 15:42

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