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I am wondering if the following statement could be supported by verilog. Basically I would like to be inside the posedge clock detection, in some cases to trigger a negedge detection as well. Is it doable?

I basically want to generate a divider (both even number and odd number). For example, for divider number of 10, I would only count the positive edge to generate a 50/50 duty cycle clock. in this case, only the positive clock edge detection is fine.

However, for divider number of 11, I would like to count the negative colck edge as well in order to generate a 50/50 duty cycle. So inside the positive clock edge detection, I would like to have a negative clock edge detection as well.

Can the negative clock edge detection be placed inside the positive clock edge detection loop?

  Always @(posedge clk) begin
     if (n=10) begin      
     always @(nededge clk) begin
          n=5;
          end
     end
     else 
     xxx
     end
endmodule
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  • \$\begingroup\$ Can you put into words what you expect this to do? Because, the always block is "executed" (not quite the right word, this isn't software!) at the edge defined, so you're writing "Always when there's a positive clock edge, do: always when there's a negative clock edge…" In other words: what you want to build is logically illegal; at that point it doesn't matter that it's also verilog-illegal. \$\endgroup\$ – Marcus Müller Sep 29 at 17:46
  • \$\begingroup\$ thanks for the comments, I add more comments to clarify the question. \$\endgroup\$ – Brian Lee Sep 29 at 17:56
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No, you can not.

what you can do is drop the 'always' and just wait for a negative clock edge:

 always @(posedge clk) 
 begin
    if (n==10) 
    begin      
       @(negedge clk) 
       begin
           n <= 5;
       end
     end
 end

Please realise that the code can only be used in a test-bench. You can not synthesize this.


Even for your code which removes always, it is still not synthesizable?

Nope! That is what I wrote. There is no single logic element that responds to both rising and falling clock edges.

All double edge logic like DDR interfaces are comprised of two sets of FFs: falling and rising edge and the results are combined. Most often transferring the falling edge data to the risign edge so you end up with double width data.

I had to fix your if (n=10) and nededge I suggest you be more careful even when making examples.

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  • \$\begingroup\$ Thank you for the comments. Even for your code which removes always, it is still not synthesizable? Thank you very much! \$\endgroup\$ – Brian Lee Sep 30 at 17:50

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