I am wondering if the following statement could be supported by verilog. Basically I would like to be inside the posedge clock detection, in some cases to trigger a negedge detection as well. Is it doable?
I basically want to generate a divider (both even number and odd number). For example, for divider number of 10, I would only count the positive edge to generate a 50/50 duty cycle clock. in this case, only the positive clock edge detection is fine.
However, for divider number of 11, I would like to count the negative colck edge as well in order to generate a 50/50 duty cycle. So inside the positive clock edge detection, I would like to have a negative clock edge detection as well.
Can the negative clock edge detection be placed inside the positive clock edge detection loop?
Always @(posedge clk) begin if (n=10) begin always @(nededge clk) begin n=5; end end else xxx end endmodule