# Verilog: negative value in brackets of vector signal definition

I am looking at the code in the following website.

https://www.csee.umbc.edu/~tinoosh/cmpe641/slides/05-Memories.pdf

In their code, they claims something like

input signed [7:-12] c_in;

I am wondering what does the negative mean in here?

module scaled_square ( output reg signed [7:-12] y,
input signed [7:-12] c_in, x,
input [11:0] i,
input start,
input clk, reset );
wire c_ram_wr;
reg c_ram_en, x_ce, mult_sel, y_ce;
reg signed [7:-12] c_out, x_out;
reg signed [7:-12] c_RAM [0:4095];
reg signed [7:-12] operand1, operand2;
parameter [1:0] step1 = 2'b00, step2 = 2'b01, step3 = 2'b10;
reg [1:0] current_state, next_state;
assign c_ram_wr = 1'b0;

• Hi! I tried to enhance the title of your question a little to make it describe your question more closely. (also, I remove the "thank you, Brian", as salutation phrases are, in the interest of conciseness, generally slightly frowned upon here) Sep 30, 2019 at 18:13

## 3 Answers

Example 1

reg [3:0] addr;

The 'addr' variable is a 4-bit vector register made up of addr[3] (the most significant bit), addr[2], addr[1], and addr[0] (the least significant bit).

Example 2

wire [-3:4] d;

The d variable is 8-bit vector net made up of d[-3] (msb), d[-2], d[-1], d[0], d[1], d[2], d[3], d[4] (lsb).

So [7:-12] c_in; would create this array of wires/integers or whatever your creating an array of:

c_in[7]
c_in[6]
c_in[5]
c_in[4]
c_in[3]
c_in[2]
c_in[1]
c_in[0]
c_in[-1]
c_in[-2]
c_in[-3]
c_in[-4]
c_in[-5]
c_in[-6]
c_in[-7]
c_in[-8]
c_in[-9]
c_in[-10]
c_in[-11]
c_in[-12]

When declaring a packed array (vector) you can declare the MSB index to the LSB index. Normal convention is for 0 to be the LSB index. This way each index bit x[N] represents the 2N-th bit. Although Verilog does not support fixed point directly, some people use a negative LSB to represent the precision of a number. So when someone declares

reg [7:-12] x;


x[7:0] is meant to be the integral part of the number, and x[-1:-12] is meant for the fractional part of the number. 2-12 is the precision of the factional part.

From the Verilog 2001 Specification:

3.3.1 Specifying vectors

The range specification gives addresses to the individual bits in a multibit net or reg. The most significant bitspecified by the msb constant expression is the left-hand value in the range and the least significant bit spec-ified by the lsb constant expression is the righthand value in the range.

Both msb constant expression and lsb constant expression shall be constant expressions. The msb and lsbconstant expressions can be any value—positive, negative, or zero. The lsb constant expression can be agreater, equal, or lesser value than msb constant expression.

Essentially the range for a vector can be any value you like, be that positive, negative, zero, LSB first, MSB first. It doesn't have any bearing on the actual output.

Using [7:-12] x is equivalent to [19:0] x in behaviour.

As to why the designer chose to use negative values in their code, that is entirely their prerogative.

• hi Tom Thanks for the comments, so in your opinion, [7:-12] x is exactly equivalent to [19:0] x, right? thank you very much, Brian Sep 30, 2019 at 22:49