In the PCI bus spec, when in the address phase of a transaction, there are extra bits for specifying the type of transaction (called C/BE). These lines are also re-used during the data phase of the transaction as byte enables.
My question is this: what is the exact series of steps for a CPU to set these bits?
Is there some memory-mapped controller on the motherboard with a register for the Address/Data pins, and a register for the C/BE pins? If so, does that mean every transaction on the PCI bus requires two writes from the CPU (one to set the address/data, another to set the C/BE pins)?