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In the PCI bus spec, when in the address phase of a transaction, there are extra bits for specifying the type of transaction (called C/BE). These lines are also re-used during the data phase of the transaction as byte enables.

My question is this: what is the exact series of steps for a CPU to set these bits?

Is there some memory-mapped controller on the motherboard with a register for the Address/Data pins, and a register for the C/BE pins? If so, does that mean every transaction on the PCI bus requires two writes from the CPU (one to set the address/data, another to set the C/BE pins)?

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  • \$\begingroup\$ This questions starts from a bit of misunderstanding: in actuality, the CPU doesn't directly talk on the PCI bus, a PCI bus bridge does that, on behalf of the CPU or peripheral to which it is connected. \$\endgroup\$ – Chris Stratton Oct 1 '19 at 15:15
  • \$\begingroup\$ As noted by Chris Stratton, the processor itself does not handle that actual transaction; there may well be a PCI controller within the silicon, but the controller actually handles the various phases of the transaction. \$\endgroup\$ – Peter Smith Oct 1 '19 at 15:42
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The CPU cannot directly control those pins. Those pins are driven by whatever device is the current bus master, which could be a PCI switch port or PCI device. In the case of an operation initiated by the CPU, this will be a PCI port on some sort of bridge chip. A bridge chip essentially performs a protocol translation. The bits will be set based on the type of operation that the CPU performs. For instance, if the CPU executes IO or memory read or write operations against the address space that corresponds to that PCI port, then the bits will be set appropriately as part of the requested operation. Config read and write operations are a bit different - either Configuration Access Mechanism (CAM) which uses IO operations, or Enhanced Configuration Access Mechanism (ECAM) which uses MMIO enables the CPU to access PCI configuration space.

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During an PCI write transfer the C/BE lines are toggled depending on what kind of transfer needs to take place (determined by the CPU, the transferring happens in the PCI host controller or north bridge). There are many assembly commands that will enable the C/BE lines during a write transfer.

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Source: http://www.soc.napier.ac.uk/~bill/comp_eng_presentation/pci_bus.pdf

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