I would like to know what would be the difference between between using "+" or writing an adder for adding two numbers:
library ieee; using ieee.std_logic_1164.all architecture one of my_adder is component f_a -- suppose we have a full adder port .... end component; FA: for i in 0 to n generate -- suppose we just carry chain the full adders FA_i: f_a PORT MAP ... end generate; end;
library ieee; using ieee.std_logic_1164.all using ieee.numeric_std.all architecture two of my_adder is out <= A + B; end;
What would be the difference? What would happen during synthesis? What would be the consequences on a FPGA?