I am going through SPI transmission for implementing in FPGA, While researching, In few articles such as
https://en.wikipedia.org/wiki/Serial_Peripheral_Interface and this https://web.archive.org/web/20150413003534/http://www.ee.nmt.edu/~teare/ee308l/datasheets/S12SPIV3.pdf Which says in Section 4.4.1
Using two bits in the SPI Control Register1, software selects one of four combinations of serial clock phase and polarity.
The CPOL clock polarity control bit specifies an active high or low clock and has no significant effect on the transmission format.
The CPHA clock phase control bit selects one of two fundamentally different transmission formats. Clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements.
My question is What is the need of specifying the different modes in SCK, Though the last line tries to reason out, It sounds vague and doesn't specify actual reason,
What is the actual reason is for specifying the SCK polarity and Phase in which mode is determined.