I'm very new to VHDL and I'm trying to design a simple clock divider process, but I'm running into a strange disparity between two forms of a process that I can't tell apart logically. I'd really appreciate help with this! Sorry if I don't include enough context, I don't know yet what would be helpful for this sort of thing.
Form 1:
div_main : process(clk_in) is
variable count : integer := 0;
begin
if (rising_edge(clk_in) and sw_in(3) = '1') then
count := count + 1;
if (count > div) then
count := 0;
tmpclk <= not tmpclk;
end if;
end if;
end process div_main;
Form 2:
div_main : process(clk_in) is
variable count : integer := 0;
begin
if (rising_edge(clk_in) and sw_in(3) = '1') then
count := count + 1;
end if;
if (count > div) then
count := 0;
tmpclk <= not tmpclk;
end if;
end process div_main;
(The sw input is a form of clk enable) (The clk_in is a 125MHZ pin output on the FPGA)
The first form works perfectly, but I'm having a ton of issues with the second. It's tmpclk output is nearly random. The only difference I can see is whether the conditional reset of count is evaluated on only rising edges or on both rising and falling edges, which I wouldn't think matters. I would really appreciate if someone could explain why they behave so differently!