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I've got some question about stack-up for 4 layer PCB.

My design is rather simple but due to many connections all arround PCB it couldn't be made with 2 layer PCB, this is why I picked 4 layer board.

My PCB is 1.6mm thick, with 1oz copper on all layers (incl. internals).

I'm using 1st layer as a power/signal layer with some locals ground pours that are connected with multiple vias to inner ground plane (which is 2nd layer // and whole 2nd layer is big ground pour without any slots [excl. vias clearance]).

Question is should I use 3rd layer as a power/signal and 4th as a big ground pour? Or should I swap it and make 3rd layer as a GND and 4th as a signal/power.

Due to many connections it's not possible to place power only traces on 3rd layer and signals on 4th because there will be some slots here and there and it will make my current loop alot longer, this is why I combined power and signal to one layer. From mechanical point of view 1st and 2nd layer are adjacent do each other, similiar for 3rd and 4th.

I'm very curious which option could be better for me - I hope some of you might help ;)

PS: all component pads are located at 1st layer, there is no MCU's or any other high speed signals like clocks etc. PCB is mostly occupied with power IC's like supervisors, LDO's and some audio stuff.

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  • \$\begingroup\$ This isn't the commonly used 4layer stackup, which means to me that there are a whole host of hints and helps you'd probably be able to benefit from. Although this isn't going to be acceptable as an SE:EE answer, go read the PCB tutorial by the EEVBlog guy: alternatezone.com/electronics/files/PCBDesignTutorialRevA.pdf \$\endgroup\$ – pgvoorhees Oct 4 '19 at 11:41
  • \$\begingroup\$ Technically - it's quite typical for me ;) 1st is signal/power which is normal for SMD parts located at the top of PCB. 2nd is ground/reference plane without slots (excl. vias clearance). 3rd could be another ground/reference plane, 4th is signal/power Question was should I swap 3rd and 4th layer and if yes I just know why should I do that ;) I'm not going to use one whole layer for power - instead of that I picked very wide traces for power. I designed my PCB with some points in mind like making signal/power adjacent to reference plane without slots that could cross those traces. \$\endgroup\$ – mikolaj612 Oct 4 '19 at 11:47
  • \$\begingroup\$ I absolutely don't mean to say that the stack is wrong. Whether a stack works is entirely dependent on your design and your product needs. The "typical" 4L stack is, top-to-bottom: Signal-GND-Powers-Signal. We can offer better help with an implementation if you want to post it. \$\endgroup\$ – pgvoorhees Oct 4 '19 at 11:54
  • \$\begingroup\$ I tried to do your stack-up, but due to plenty of slots I decided to abandon that idea. When 3rd layer was occupied by power traces or pours then rest of my signals came from top to bottom - and I could live with that, except those slots I made while partitioning power layer :( So I decide to combine power and signal to one layer - because of that I've got possibility to make one internal or external layer to be reference/ground plane without any cutouts/slots. Just trying to learn a little bit more about stack-ups and potential advantages ;) Anyway thank you for help, \$\endgroup\$ – mikolaj612 Oct 4 '19 at 12:01
  • \$\begingroup\$ Well, I'll say this, unless you are trying for some insanely high SNR or high speed (Ghz) clock speeds, it doesn't sound like you need to worry about the stackup. Depending on what you mean by "power ic's" you may need thicker layers. Once you have a design laid out, you can always post it and we can talk specifics though. \$\endgroup\$ – pgvoorhees Oct 4 '19 at 12:05
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I would go with this :

  1. Signal - Power
  2. Ground
  3. Power distribution & ground
  4. Signal - power

Signal on top is obvious, it is to avoid vias as much as possible.

Ground on layer 2 is obvious too.

I usually use Layer 3 for power distribution, it helps a ton to keep the signal layer as clean as possible, and allows optimal routing of power traces.

I try to avoid inner signal traces, it makes debugging & rework much harder than needed, so layer 4 is for signal.

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  • \$\begingroup\$ I'm unable to do that. If I split power and signal from layer 3 to 3 and 4 there will be plenty of slots on 3rd layer, there is no logical way to fill it with copper or to route traces without making slots for current return for 4th layer (signal). I've got an idea, how about route signal/power at 1st layer, 2nd and 3rd will be REF/GND and 4th will be signal/power. But I could use burried vias to connect inner layers together. \$\endgroup\$ – mikolaj612 Oct 4 '19 at 14:07
  • \$\begingroup\$ you can fill Layer 3 with ground or ref plane, that is a good plan. but unless they are REALLY necessary, try to avoid buried vias, because they will increase the cost of your board (and by increase, i mean skyrocket) \$\endgroup\$ – Sclrx Oct 4 '19 at 14:13
  • \$\begingroup\$ This is my only option to do adjacent plane for signal/power without slots. I could fill 3rd layer or 4th - my concern here is which one will be better. About burried vias I need to ask my supplier about availability and costs. Technically it would be great to connect inner reference planes together with plenty of those vias. It will mostly decrease current loops for signals routed from top to bottom and vice versa - am I right? \$\endgroup\$ – mikolaj612 Oct 4 '19 at 14:16
  • \$\begingroup\$ BTW I assume if I use inner layers for REF/GND there is no reason to fill bottom layer (where signal and power traces will be routed) with GND? I could do that, but question is it worth it? \$\endgroup\$ – mikolaj612 Oct 4 '19 at 14:20
  • \$\begingroup\$ @mikolaj612 What do you mean by slots? If you are doing a split plane, slots are normal. Just don't route high speed tracks across them. \$\endgroup\$ – The Photon Oct 4 '19 at 15:01
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Question is should I use 3rd layer as a power/signal and 4th as a big ground pour? Or should I swap it and make 3rd layer as a GND and 4th as a signal/power.

It is usually better to put the a solid GND on one of the inner layers.

1) it facilitates a nice ground plane and creates a small amount of capacitance between the traces on the outer layer, which is nice for high speed signals and transmission lines. 2) A solid ground reduces common mode noise from return currents. If you ran a network of traces the resistance in the traces could create a voltage noise from switching current or large currents. Because of this we use a nice big solid plane that lowers the resistance between all components connected to it.

It's also a good idea to have large traces for power, reducing resistance and inductance. A better idea is to have planes.

It's really up to you how the layers go and what kind of design it is. The best way is to use a PCB trace calculator to give you an idea of what the resistance and inductance is of the PCB copper.

Some designs must use shielding, and use grounds on the outside and power and signal on the inside.

The typical stackup looks like this:

1) signal
2) GND
3) Power\Signal\GND
4) Power\Signal

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  • \$\begingroup\$ My possibilites are : 1st layer signal and some power traces, 2nd layer whole filled with GND, 3rd layer could be combined power and signal (rest of signals that could not been routed on top), 4 layer is available then for reference, But I could swap them as a option. Technically I could route power traces on 3rd layer and fill rest space with GND (because most space will be empty anyway), Then 4th layer is available for signal only. Hard to tell which one is best option. \$\endgroup\$ – mikolaj612 Oct 4 '19 at 16:30
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it's not possible to place power only traces on 3rd layer and signals on 4th because there will be some slots here and there and it will make my current loop alot longer.

Try this:

1 : Components, short traces (10 mm or less, say)

2 : Power

3 : Ground

4 : Any length traces

By using 1 and 4 as trace layers; and 2 and 3 as plane layers you make a symmetric stack-up which is less prone to warping.

By putting your ground on layer 3 and long traces on 4 you avoid routing long traces across the slots in your power plane.

By restricting layer 1 to short traces you avoid routing long traces across the slots in the power plane. In any case it's often difficult to route long traces on layer 1 due to components getting in the way.

In this scheme, "traces" can include both signal and power routing, but of course you'll want to minimize the use of traces for power to keep the inductance low.

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