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I'm working on a PCB which is basically multiple MCP23017 GPIO expanders driven from I2C. As I layout the board (in EAGLE), I frequently find places where using different IO pins would avoid vias and other routing complications.

But of course, the standard library part for this device doesn't allow pin-swapping, because that would be a functional change in the design. In my case, I'm also writing the software to drive the I2C, and in most cases, it's a simple re-ordering in code, to use a different pin - so it would be no problem for me.

(Especially since the MCP23017 allows pin-level selection of in/out mode)

Given this, is there a way to achieve pin-swap like functionality when laying out? Going back into to the schematic to adjust things manually is awkward but what I have been doing so far. I'm aware I could clone the part into a local library and edit the pins to enable pin-swap, are there any drawbacks or downsides to this?

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  • \$\begingroup\$ In my experience just changing the schematic is the cleanest. Sometimes pin swapping makes a mess on the schematic. \$\endgroup\$ – MadHatter Oct 5 at 19:06
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The bottom line here is that you always want your schematic to exactly represent your design. A pin swap function in the layout package still needs to be able to back annotate into the schematic so that the schematic accurately represents the layout design. That can work out nice in that this back annotate function can automate some of the schematic update work.

I suggest that trying to enable pin swap in the I/O Expander may not be ideal. Pin swapping really is aimed at pins which are exactly functionally equivalent. Your I/O Expander pins are not really following this as there is an internal register interface difference between a GPB4 and a GPA6 pin. One usually tends to draw the symbol for a part like the I/O Expander so that the "port sets" of pins (i.e. all the GPA or GPB groups) are grouped together in bit order so that it is easy to visualize the connections from the schematic to the software. Some of this visualization seems like it will be lost when pin swaps would occur. The worst case of this is when a subgroup of the I/O pins are used together in a weighted binary group. For example GPB[2::0] used to connect to the A{2::0} selector pins of a 8 to 1 selector chip.

For your general usage of multiple I/O Expanders it is highly likely that there can be layout optimizations to swapping GPIO connections between different components. A layout package's pin swapping function is not going to support this type of swap and you would be back to doing the back annotation into the schematic manually for this case.

I suggest to just go ahead and swap your net list connections manually in the layout package and mark up accordingly on your paper working copy of the schematic. Once you have completed the layout you can go to manually back annotate into the schematic all at once. One good suggestion is that you have all of the nets be named in the design with names that you have edited rather than leaving some to be autonamed by the design tools. The reason for this is that with auto named nets you will likely have name collisions or missing name problems next time you revise your schematic and want to re-import the net list back into the schematic.

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