# How to get a 1 clock period pulse from a constant input? [duplicate]

I want to make a digital circuit that produces a pulse 1 clock period in duration whenever I see the input to the circuit go HIGH. I only have a flip-flop, an AND-gate, and an inverter. How do I achieve this?

I'm familiar with edge detector circuits like the ones seen here, but such circuits don't necessarily produce an output that lasts for 1 clock period.

My first attempt at a solution was the Rising Edge Detector circuit found in the linked above document. Here's the picture:

However, this circuit will not produce a pulse of sufficient duration:

The stage after this circuit is a counter that should increment when it is enabled by the pulse generated in the circuit to be designed.

Edit: This problem cannot be solved by a traditional edge detector circuit since it doesn't produce a 1 clock cycle duration pulse.

• @VoltageSpike No, look at the logic outputs of the solutions. None of them are 1 clock period in duration. – user50420 Oct 5 '19 at 21:24
• Why are you restricted to one FF, one AND gate, and one inverter? This sounds like it could be a homework problem. – Elliot Alderson Oct 5 '19 at 21:45
• I'm voting to close this question as off-topic because it is a homework question with no attempt at a solution. – Elliot Alderson Oct 5 '19 at 21:56
• If it is a homework problem, state that it is a homework problem in the main question (please edit the question to add this). Also, please include the full statement of the problem (again, edit the question to add this information) so we know all the constraints. – mkeith Oct 5 '19 at 22:11
• Here is an example: what if I suggested that you use a T flip flop instead of a D flip flop. then you said "No, it has to be a D flip flop." OK, but you didn't say that in the question. So now you just caused me frustration. This is just a made up example providing the rationale for why people ask you to do certain things. It is made up but based on true events that happen here every day. – mkeith Oct 5 '19 at 22:34

If the input is asynchronous with respect to the clock, it can't be done with a single flip-flop.

It's easy to show that an abstract state machine that implements the specification needs to have at least three states:

1. Before the pulse
2. During the pulse
3. After the pulse

You can't implement a 3-state machine with only a single flip-flop.

If the input is synchronous with the clock, then that needs to be stated as part of the problem. Then you can use the input signal directly to generate one of the output pulse edges, as in your Figure 1.

• Good answer. I upvoted it. An observation: If the input is synchronous with the clock, that essentially suggests that there is another flip flop somewhere else. It is almost like there have to be two FF's. Period. – mkeith Oct 6 '19 at 5:29