I'm designing a rather big PCB which will have 64 nokia 5110 LCDs arranged in an 8x8 matrix and will all be controlled by a single microcontroller.
Each screen will have an 8-bit shift register as a buffer, to compensate for the mismatch between the microcontrollers ~50MHz max SPI clock and the LCDs 4MHz. Therefore, there will be 64 shift registers in series at 50MHz on an approximately 30cm x 30cm PCB.
My question is then, what are the problems I should account for in such a design? Assuming I place each screens shift register behind it, I would have really long (approximately 250cm) zig-zagging traces for the clock and data lines.
This seems pretty ridiculous, but at the same time I've had no problem working with breadboard and jumper wires at close to those frequencies, the only difference being the wire length.
I could also clump all the shift registers near the microcontroller so the longest lines will be the ones leading into the screens at the lower frequency, but the traces would still be pretty long.
I'd appreciate any help and suggestions to avoid having many failed PCB designs.