I'm designing a rather big PCB which will have 64 nokia 5110 LCDs arranged in an 8x8 matrix and will all be controlled by a single microcontroller.

Each screen will have an 8-bit shift register as a buffer, to compensate for the mismatch between the microcontrollers ~50MHz max SPI clock and the LCDs 4MHz. Therefore, there will be 64 shift registers in series at 50MHz on an approximately 30cm x 30cm PCB.

My question is then, what are the problems I should account for in such a design? Assuming I place each screens shift register behind it, I would have really long (approximately 250cm) zig-zagging traces for the clock and data lines.

This seems pretty ridiculous, but at the same time I've had no problem working with breadboard and jumper wires at close to those frequencies, the only difference being the wire length.

I could also clump all the shift registers near the microcontroller so the longest lines will be the ones leading into the screens at the lower frequency, but the traces would still be pretty long.

I'd appreciate any help and suggestions to avoid having many failed PCB designs.

  • \$\begingroup\$ What micro controller? What buffer? Usually the largest limiting factor is capacitance, and then actually driving the GPIO to achieve 50MHz \$\endgroup\$
    – Voltage Spike
    Oct 5, 2019 at 22:25

3 Answers 3


At 50MHz, the wavelength in the PCB is about 20ns x 15cm/ns = 300cm.

The time of travel in a wire of 30cm is 2ns.

If you want to avoid to consider you traces as transmission lines, you must keep them under 1/20th of the wavelength, which is 15cm.

And at that length you need to account for the 1ns signal delay when checking hold and checkup times.

You also need to avoid crosstalk between parallel wires by keeping them 3x their width apart.

  • \$\begingroup\$ The rise/fall time of the signals will probably be much more important than the actual toggle rate. \$\endgroup\$
    – user4574
    Oct 6, 2019 at 0:44
  • \$\begingroup\$ If the signal lines are kept under 15cm, the rise/fall time will be within bounds. It is clear that distributing a central clock is excluded with this limit. There are "shift" solutions that also buffer the clock on each clock. And when using a manchester encoding for instance, it would be possible to buffer the signal every 15 cm using a simple digital buffer. \$\endgroup\$
    – le_top
    Oct 6, 2019 at 0:51

I would route the high frequency signals as controlled impedance.

I would also add a termination resistor to each signal to avoid reflections. You can either user series termination at the source of each signal or use parallel termination at the destination of each signal.

Also, the 50MHz signal period is much less likely to be a problem than the rise/fall time of the signals. If you can keep the rise/fall times slower it will help avoid reflections.

Assuming your shift registers only shift on a clock edge, then the most important signal to consider will be the clock signal on the shift registers. Even if you get reflections on the data lines it probably won't matter as long as the signals settle to their final value before the next clock edge. But if you get a reflection on the clock then your shift register may see two or three clocks and all of your data will be shifted over.


My question is then, what are the problems I should account for in such a design?

In my designs with an STM32F it can be difficult to reach 50MHz. The first problem will be GPIO capacitance, it may be problematic with the capacitance of the GPIO's themselves even with short runs, the gate capacitance of the receiving port must also be taken into consideration.

The other problem is a very fast microprocessor if bit banging. If not bit-banging then you will need to use SPI hardware ports.

I have a hard time believing that you can achieve 50MHz on a breadboard, but it depends on the setup (I'd like to see a scope trace and pic of the setup). If the design works on a bread board, the parasitics are much smaller on a PCB, so theoretically you should have minimal problems if you move it over to a PCB.

Use a 4 layer design with the clock on the top, not running through vias and ground on the layer directly below.

  • \$\begingroup\$ With your answer and what others have also commented I'm leaning away from my original idea and rethinking my approach. I'm planning on using hardware SPI, I already made some basic circuits and got it working well. As for the breadboard I've gotten to 36MHz (with a pretty gnarly waveform though but all data was received), not exactly 50MHz but pretty close, with the difference that the wires were at most 10cm long. My original question was prompted from the fact that in the PCB the traces would be SO much longer than what I was used to. \$\endgroup\$
    – jjpprr
    Oct 8, 2019 at 22:51

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge that you have read and understand our privacy policy and code of conduct.

Not the answer you're looking for? Browse other questions tagged or ask your own question.