Clock Multiplier / Clock Boosting

Question

I was reading this paper "A 10 b, 20 Msample/s, 35 mW Pipeline A/D Converter" by Cho and Gray from 1995. https://ieeexplore.ieee.org/document/364429

In it, they describe a clock multiplier circuit with two capacitors (on the charge pump principle):

My understanding of this is as follows:

During the 0 to 3.3V initial phase of the clock

1. C1 and C2 are completely discharged and thus appear as shorts. The inverter causes a logic high to appear at the gate of the left transistor, turning it on. Source of M1 (output) sees 3.3V
2. C1 is charged to 3.3V through the left transistor.
3. Due to C1 being at 3.3V, the right transistor now turns on and causes 3.3V to appear at the source of M1 (output)

Now from this explanation, the output node (source of M1) is at 3.3V? How does he get a square wave going from 0V to 5V?

Answer 1

C2 is charged to 3.3V when the clock is high.

When the clock goes low the lower end of C2 (attached to the inverter) goes to 3.3V. This causes the source of M1 to rise (potentially to 6.6V but parasitic capacitances will cause it to be lower). This will pass through M1 to the output node.

When the clock is low the transistor to the left and right of M1 will both be off.

Be careful about terminology - a clock multiplier is usually interpreted meaning the frequency of the clock is multiplied, not its voltage.