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I write a piece of Verilog code:

module hBit ( dataOut, dataIn, read);
output dataOut;
input dataIn, read;
wire bitValue;

pmos( bitValue, read, bitValue);
nmos( bitValue, read, dataIn);
assign dataOut = bitValue;

endmodule;

which I think could be implemented by the circuit in the left side of the attached schematic. But a huge problem is that the signal stored in hBit deteriorates with time. So in the circuit on the right side of the schematic I added a step where the signal either remains low (for a logical zero) or it gets amplified to a high voltage (for a logical one). Note that this circuit includes a resistor in between the voltage source and ground, to avoid a short circuit when the additional transistor conducts.

My question is, how can I represent the circuit on the right with Verilog? Is there a way to represent a resistor in Verilog?

schematic

simulate this circuit – Schematic created using CircuitLab

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2 Answers 2

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You can't represent arbitrary resistors in verilog as resistors are analog and verilog is digital (as opposed to verilog-a, which is analog). However, you can model pull-ups with the pullup primitive, like this:

pullup p (some_signal);

There is also a similar pulldown primitive that pulls to 0 instead of 1:

pulldown p (some_signal);
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You can model pullup and pulldown resistors using Verilog pullup and pulldown primitives.

module hBit ( 
             output dataOut,
             input dataIn, read)
trireg bitValue; // used for modeling charge decay

nmos M3( bitValue, dataIn, read);
pmos M4( dataOut, bitValue, read);
pmos M5( dataOut, 0, bitValue);
pullup R1(dataOut);

endmodule;

There is also a trireg wire type to module capacitive discharge and resistive rcmos and rpmos primitives. But these are very crude digital approximations for analog behavior.

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  • \$\begingroup\$ Is this a typo? Logical value (dataOut) is listed as the first port to (M4), and it's also listed as the first port to (M5), both of which are PMOSes. In the first case it's an input; in the second case it's an output. Why would a port in the same position be an input once and an output the other time? \$\endgroup\$
    – KevinSim
    Commented Oct 18, 2019 at 0:29
  • \$\begingroup\$ Yes, that was a typo. Fixed. Didn't test this, but I hope you got the point about the pullup/down in place of resistors. \$\endgroup\$
    – dave_59
    Commented Oct 18, 2019 at 5:46
  • \$\begingroup\$ Now I'm really confused. Is the first port of a PMOS an output or an input? If it's an output, how can it be a logical zero? \$\endgroup\$
    – KevinSim
    Commented Oct 18, 2019 at 16:02
  • \$\begingroup\$ I'm truly sorry for confusing you. I had my pmos ports mixed up. It should always be pmos(source, drain, gate). This was incorrect in your original post \$\endgroup\$
    – dave_59
    Commented Oct 18, 2019 at 22:43
  • \$\begingroup\$ Then wouldn't the first transistor invocation be:"pmos M4( bitValue, dataOut, read);"? \$\endgroup\$
    – KevinSim
    Commented Oct 19, 2019 at 2:09

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