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I was trying to design an arbiter puf in SPARTAN 3E while doing that one need to connect d flip flop at last. Problem was that one of the mux output is to be connected to d flip flop which is giving IOB error says clock position is not optimal. But I can't give clock pin number C9 which is inbuilt clock in SPARTAN 3E as it need to come from one of the mux. How to solve this problem considering that I want to use 40 such parallel block. One of block in shown in figure?enter image description here I am trying to run a verilog code of following design in figure where there are two pair of muxes and flip flop to make an arbiter puf. I don't understaand how to correct the error.

module arb(a,en,b,qq );input a,en,b;
output  qq;
wire y;
wire p,q,r,s;
mux m0(en,en,a,p);
mux m1(en,en,a,q);
mux m2(p,q,b,r);
mux m3(q,p,b,s);
dff d1(r,s,y);
assign qq=y;  endmodule

module mux(input a,b,s,output q

);
assign q=s?b:a; endmodule

module dff(input d,clk,output reg q

);
always@(posedge clk)
q<=d; endmodule

I am getting error Error message is Place:1018-A clock IOB/ clock component pair have been foundthat are not placed at an optimal clock IOB / clock site pair. The clock component is placed at site .The IO component is placed at site . This will not allow the use of fast path between the IO and the Clock buffer. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED _ROUTE constraint in the .ucf file to denote this message to a warning and allow your design to continue.However,the use of this override is highly discouraged as it may lead to a very poor timing results.It is recommended that this error error condition be corrected in the design. A list of all the COMP.PINs used in this clock placement rule is listed below.These examples can be used directly in the .ucf file to override this clock rule.

This error is in place and route option in SPARTAN 3E

So my question in how to write verilog code of given figure and still don't get error

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1 Answer 1

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Although this comes out as an error, I interpret it as a (severe) warning.

Short:
It means that you will have additional skew between clocks on your design. That may cause issues if you want to clock registers with that (delayed) clock.

Long:
Clocks internally come from a global clock buffer. From there a special clock net is routed to all corners of the FPGA such that it reaches all register with minimum skew. The input of these clock buffers can some from a special short path to a number of dedicated I/O pins.

Now you want to clock a register from a clock you made yourself*. That clock first has to be routed to the input of a global clock buffer. And that is where things go wrong. It will takes a relative long time for the signal to reach the clock buffer. Then the signal has to go through the buffer, after which it has to be distributed over the chip again. In many, many cases this clock skew cause circuits to fail. Especially as this clock skew is not present in your test-bench and thus your simulations may look fine but your circuit has a high probability to fail.

*By the way: that is generally a very, very bad idea! I have rarely seen a circuit where that is really needed. In 99% of the time it is just a bad or sloppy design and there are better, synchronous solutions.

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  • \$\begingroup\$ Please can you elaborate how would you design above diagram in SPARTAN 3E showing your .ucf file . Where you would place mux output which is connected to clock. \$\endgroup\$
    – mohit
    Commented Oct 8, 2019 at 7:10
  • \$\begingroup\$ You do not fix that in the UCF, you fix it in the source code. Looking at your diagram a simple if (..) is probably all you need. You could make a new question showing the source code with the clock gating and ask the community how to avoid it. \$\endgroup\$
    – Oldfart
    Commented Oct 8, 2019 at 7:28
  • \$\begingroup\$ find error in code and tell proper code? \$\endgroup\$
    – mohit
    Commented Oct 8, 2019 at 9:15

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