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I use some decoupling capacitors (100 nF) for low speed ICs (< 1 MHz) and I need some recommendations to verify my routing. My layout uses two layers:

  • Top (Red) with Vcc
  • Bottom (Green) with GND

And I have this IC as an example:

enter image description here

enter image description here

The Vcc layer is connected to my cap and the cap is connected to the IC over pin 28. So the IC is directly connected with the cap and not with the layer.

Here is the question: Should I do the same for the ground connection or is it fine to connect the cap as shown in the image? The "bad" thing with DIP-packages is the long routing distance between GND and Vcc (pin 14 and pin 28) for example. Then the next question is how do I handle decoupling capactitors for ICs like the FT232RL which has more GND than Vcc pin. Should I connect all GNDs and route them to the GND of the cap or can I connect them directly with GND.

What is a smart way to do it?

Update: Add the changes enter image description here

enter image description here

enter image description here

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Considering the small green traces leaving pins 15 to 21 at the south side, you probably have completely cut the ground plane connection to pin 22 and pin 14.
It looks like the ground connection from the capacitor to pin 28 runs (way) south of pins 15 to 28, heading north, west of the IC. (Or it runs way east of IC). Anyway, with such a long trace, I doubt the capacitor functions as a decoupling capacitor.

I would recommend to delete all the Vcc polygons/plane, try to swap the mentioned bottom traces (originating from pins 15-21) to the top and apply a decent (uninterupted) ground plane in the bottom layer.
Only when necessary (when traces have to cross other traces), use a vias to swap the trace to the bottom side, but keep those bottom traces as short as possible.

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  • \$\begingroup\$ Uhh okay. This would result in a big redesign, but thanks. I will try it. \$\endgroup\$ – Kampi Oct 8 at 10:43
  • \$\begingroup\$ @Kampi I wouldn't change that fast. Seeing your updated question, you may as well make a thick trace on the top layer from pin 22 heading north, ending on a via (near the silk text IC5), to connect it to green ground plane/polygon. That way you reduce the connection between the ground planes. Not most optimal, but might be enough when signals are not that fast. \$\endgroup\$ – Huisman Oct 8 at 11:02
  • \$\begingroup\$ Yeah you are right. I reorder some traces so optimize the ground plane. \$\endgroup\$ – Kampi Oct 8 at 12:07
  • \$\begingroup\$ Please check my updated answer. \$\endgroup\$ – Kampi Oct 8 at 12:36
  • \$\begingroup\$ Looks very good! I think there is a small improvement: the trace originating from pin 23 heading north on the top layer splits into a trace going west and a trace on the bottom layer. I think you can delete the bottom trace. The trace that is heading west to the via can be continued from there on the top layer going north and then east \$\endgroup\$ – Huisman Oct 8 at 16:13

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