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I'm trying to simulate for Phase Frequency Detector with the following implementation: enter image description here

and inside NAND_PFD: enter image description here

NOTE: the triangles on the right are inverters and not amplifiers.

I'm currently getting a \$Clk_{ref}\rightarrow{Up}\$ delays which are represented in this sumulation: enter image description here

same for \$Clk_{Vco}\rightarrow{Down}\$.

\$Clk_{Vco}\$ is the voltage that should come out of the VCO in a general PLL. here I picked a frequency just for simulation.

looking at the sate machine:

enter image description here

when \$ Up = Down = 0 \$ and \$ Clk_{Vco} \$ goes up, \$ Down \$ should go up. in most articles that I've read, this change appears exactly in the area of phase difference, which appears that the change is immediate and without delay.like in this image: enter image description here

how can we interpret this delay in terms of phase detection? should the phase detection appear exactly at the same time \$ Up/Down \$ change? or we just need the information of the widths of change and deliver that to the PLL to do it's job and it doesn't matter when we detected the change?

here is a longer simulation of which I'm trying to verify that the pattern of phase detecting right: enter image description here

the transistors sizing was done as the following:

enter image description here

by using ESDnfet, and ESDpfet transistors in 28n technology, with a library called cmos32lp. (in virtuoso).

Note: I still don't know what ESDnfet and ESDpfet mean, and I randomly picked them and I would be glad if someone knows this library can tell me if picking other kind of transistors would make a difference.

\$ Clk_{Vco} \$ and \$ Clk_{ref} \$ were defined as the following:

enter image description here

enter image description here

enter image description here

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    \$\begingroup\$ 1) explain why you think that there should not be any delay between the signals 2a) Cref and Cout aren't capacitors, they're voltages. Call then Vref and Vout instead. 2b) What if a NAND gate had a delay of 1 second, would that affect the maximum frequency at which the circuit can operate at? +1 for providing all needed details in your question. \$\endgroup\$ Oct 8, 2019 at 12:48
  • \$\begingroup\$ How's a delay of less than one nanosecond "huge"? These are pretty fast gates you are simulating there. The real thing with 74HC gates would be about 10 times slower. \$\endgroup\$
    – Janka
    Oct 8, 2019 at 13:04
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    \$\begingroup\$ As long as signals are propagating through real logic gates there will be some delay from the input events to the change in an output. Timing diagrams like the one you added are generally assumed to be ideal and do not reflect actual delays. \$\endgroup\$ Oct 8, 2019 at 13:33
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    \$\begingroup\$ For minimal delays , use Current Mode Logic (CML) \$\endgroup\$ Oct 8, 2019 at 13:40
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    \$\begingroup\$ using ESDnfet, and ESDpfet transistors Sounds like these are transistors which have some form of ESD protection and/or are used as ESD protection. You should not use these in a typical design. Randomly picking a component isn't how a good designer works, so read the manual and pick the right components. Use "nfet" and "pfet" instead. Read about ESD here: en.wikipedia.org/wiki/Electrostatic_discharge \$\endgroup\$ Oct 8, 2019 at 14:08

2 Answers 2

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I'm not going to work through the details of your specific schematic. I just want to make a few general statements:

  • As long as the transfer function of your detector is monotonic, it can be used to drive the frequency error of your PLL to zero. The input-to-output delay of the detector doesn't affect this.

  • As long as the delays from the two inputs to the output are matched, you can also drive the phase error to zero. If not, you're left with a small residual constant phase error, which can usually be compensated for by other means.

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  • \$\begingroup\$ first of all thanks for the reply! I attached a new simulation that shows a monotonic increase in the width of the UP signal. I need to think about this result and the delay matching that you talked about. I still can't explain why Up starts with 1.9 v. by the way, if we're already talking about this, in this case, I should always expect a periodic behavior of up signal over time, which means, I'm not expecting that Down starts have increasing widths all of a sudden (except in case the input frequencies themselves change over time, for example, Vco signal which is affected by temperature) \$\endgroup\$ Oct 8, 2019 at 14:54
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Lets experiment.

To better understand the behavior, set your Fref input to 300MHz at 50% duty-cycle with 0.3nanosecond Trise/Tfall; set your Fvar input to 310MHz input at 45% duty-cycle with 0.4 nanosecond Trise/Tfall.

Notice these are not the same frequency, so your output waveform (the UP and the DOWN pulses) will display a beatnote at 10MHz or 100 nanosecond. At various time-alignments, your output pulses will become trash. For a tight phaselock, you want the region of TRASH to be as narrow as possible, which requires the crucial gates be as fast as possible. Not all gates are crucial.

Out of 100nanosecond (1/10Mhz) observation window, you will have 30+ testing events. You can probably raise the testing frequency to 600 and 610MHz, or even to 1,000 and 1,010 MHz. Experiment with duty cycle and rise/fall times.

Now you need to understand what best drives your ChargePump, for best rectangular current switching.

And you should ask your system-people what residual phasenoise floor is needed, and then collaborate with them on how a time-edge-wander of 100 picosecond random RMS will degrade your phasenoise floor.

Lets predict the phase noise. I see 3 gates delay, plus the output buffer, for the leading edge. Assume gate bandwidth is 40GigaHertz. Assume the equivalent Rnoise in each gate&buffer is 10,000 ohms (could be lower). What is the total integrated Vnoise voltage in each gate?

Vnoise = sqrt(40,000,000,000) * 12 nanoVolts/rtHz at 10Kohms

Vnoise = 2e+5 * 12e-9 = 24e(+5-9) = 24e-4 = 2.4e-3 = 2.4 milliVolts.

The Time Jitter per gate is Vnoise/Slewrate.

Assume SlewRate is 2 volts in 20 picoSeconds, or 100Billion volts per second or 1e+11 volts/second.

TimeJitter Tj is Vnoise/Slewrate = 2.4e-3/1e+11 = 2.4e-14 = 24 femtoSeconds

per gate/buffer.

With Four gates/buffers in the path to create the initial edge of output pulses, your variance increases by 4, and your RMS ( the standard deviation) increases by sqrt(4) or factor of 2.

Thus TimeJitter is sqrt(4) * 24 femtoSeconds, = 50 femtoSeconds RMS.

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  • \$\begingroup\$ here is what I got: imgur.com/KiL4wPc can you explain further what is beatnote? \$\endgroup\$ Oct 8, 2019 at 15:23
  • \$\begingroup\$ The middle waveform seems to start repeating, at 87 nanoseconds. Is this a transistor-level simulation? or a gate-level? of course with 100Billion volt/second edges, most any simulation will seem like gate-level. If transistor-level sim, then increase to 1,000MHz and 1,005MHz and run the simulation for 200 nanoSeconds; we want to observe failure of the logic, when output pulses FAIL to reach full height; we want to break the logic behavior and start to see the transistor behavior. \$\endgroup\$ Oct 8, 2019 at 15:36
  • \$\begingroup\$ this is transistor level. here is the new simulation with 1000Mhz and 1005Mhz: imgur.com/ZQ4Wqh5, I think what we're trying to observe is the width of the pulse, that will determine and affect the charge pump functioning. are you trying to observe the deadzone range? \$\endgroup\$ Oct 8, 2019 at 15:55
  • \$\begingroup\$ yes --- trying to find incomplete-swing less-than-full-height pulses. I see none. Of course the Charge Pump may not respond to 50 picoSecond pulses. \$\endgroup\$ Oct 9, 2019 at 3:46

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