I've been given the task to make a 2-bit adder by programming a FPGA. The FPGA is seen below:

However, I don't even know how to begin this task, because I don't understand what I am looking at.

What are all those green lines supposed to do, and what about those green and red shapes?

I hope someone can clarify this for me, since I really want to understand it.

enter image description here

PS: I don't know if it is essential in understanding what's going on, but this figure was included in the problemsheet as well:

enter image description here

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    \$\begingroup\$ Welcome to EE.SE! This appears to be a homework question. As such, you need to show us your work so far, and explain which part of the question you're having trouble with. For future reference: Homework questions on EE.SE enjoy/suffer a special treatment. We don't provide complete answers, we only provide hints or Socratic questions, and only when you have demonstrated sufficient effort of your own. Otherwise, we would be doing you a disservice, and getting swamped by homework questions at the same time. See also here. \$\endgroup\$ – Dave Tweed Oct 8 '19 at 19:33
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    \$\begingroup\$ @DaveTweed Although this is a homework question, it is not the typical homework question. I think it's perfectly fine as is. \$\endgroup\$ – DKNguyen Oct 8 '19 at 19:42
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    \$\begingroup\$ Yes, but the OP is asking for information that should have already been given as part of the course. We shouldn't be needing to explain it again. \$\endgroup\$ – Dave Tweed Oct 8 '19 at 19:45
  • \$\begingroup\$ Typically you program an FPGA using an HDL (e.g. Verilog) and the manufacturer's toolchain, and never have to look at anything like what you have posted, \$\endgroup\$ – OrangeDog Oct 9 '19 at 11:33
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    \$\begingroup\$ @OrangeDog Sure, but it's convenient to have it seen at least once in your lifetime. The basic LUT architecture in an FPGA hasn't changed in over a decade, and having seen it makes it easier to see why for example having more pipeline stages in a computational path generally won't require more resources. \$\endgroup\$ – DonFusili Oct 9 '19 at 12:49

The green boxes are IO pins, the blue lines are wires, the red boxes are configuration bits, and the grey boxes are logic blocks. The red boxes can supply a constant logic 0 or logic 1 to whatever they're connected to.

Each logic block implements a 3 input, 1 output look-up table (the combination of the logic levels of the three inputs determines which of the eight configuration bits is selected) and has a bypassable flip-flop. Your post also shows the truth table that the LUT implements, indicating which configuration bit is selected for each combination of s0, s1, and s2.

For example, the red boxes at the intersections of the blue wires are connected to pass gates between the wires. Setting one of those to 1 will connect the horizontal and vertical wires together, setting it to 0 leaves the wires disconnected.

What you need to do is write a 1 or a 0 in each red box so that the input signals in the green boxes at the top get sent through the logic blocks, which you'll need to configure to implement the necessary logic to perform the operation. Looks like they want you to add {a1, a0}, {b1, b0}, and ci together.

Here's an example of how you can implement a 3 input OR gate:

OR gate

All blank boxes are assumed to be logic 0. This takes the 3 inputs a0 b0 and ci, computes the logical OR, and outputs the result on a free pin. The main things to note are how the configuration bits control the pass gates to connect the three input signals to the three inputs on the logic block and the output to a free output pin, and how the logic block implements the OR functionality - 0 when all inputs are 0, otherwise 1, with the flip-flop bypassed.

  • \$\begingroup\$ Usually there is more connecting logic from the internal buses of an FPGA, to the I/O pins, typically the I/O can be routed to almost any I/O pin \$\endgroup\$ – Voltage Spike Oct 8 '19 at 19:42
  • \$\begingroup\$ @VoltageSpike True, but this is a highly simplified example. And in this case, you might not even consider those as being IO to the outside world, but connections to some other part of a larger design. \$\endgroup\$ – alex.forencich Oct 9 '19 at 18:42

You posted your own explanation. Take a closer look at your own image:

enter image description here

The red box is meant as a label box for you to write into with a value or signal, and represents the signal that controls the switch that connects a horizontal wire with a vertical wire (the green lines). The horizontal wires and vertical wires are not connected at the junction when they cross unless the switch (transistor controlled by the value in the red box) does it


The green lines are wires, the red boxes are connections, you can connect a green wire to a block with a switch. The switch is in the red block and it can connect two wires together if enabled.

This is how many modern FPGA's work. But instead of having to do this by hand, a hardware synthesizer figures it out for you. Heck, by the time you finish this assignment, you could write your own basic hardware synthesizer!

  • \$\begingroup\$ Hmm, okay but I still don't quite get it. Most of these green wires just go from one end to another without going into any blocks. But maybe they aren't supposed to? Furthemore, what are those letters in the green shapes at the top supposed to mean? \$\endgroup\$ – Carl Oct 8 '19 at 18:43
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    \$\begingroup\$ Those are the inputs so your given three inputs, like you would in any 2 bit adder, and then you need to use the hardware you have to generate the appropriate outputs. Like this, but with FPGA hardware electronics.stackexchange.com/questions/129549/… \$\endgroup\$ – Voltage Spike Oct 8 '19 at 18:46

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