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My application, shown in the diagram below, will have 12V/GND control lines that will arrive at the gate input pins as 'high' state or 'low' state. Datasheets has two values for input current: 10mA (max rating) and 0.1uA (as static characteristics).

The external board switches belong to a board that has been used for many years and cannot be modified. The switched signals (between ground or high Z) will are connected to the gates board by a connector. Every gate input has its own pull up resistor that will connect to the switch after boards interconnection.

I focused the discussion on any pins input current. I would like to know the correct way to understand this information and whether I am handling it correctly.

My question is: What is the proper pullup resistor value in order to limit the current as is needed.

schematic

simulate this circuit – Schematic created using CircuitLab

I have chosen logic gate devices in order to work with input voltages as 12V: NOR, AND, NOT, etc. When reading datasheet I can see the maximum ratings and electrical characteristics tables. This is an OR datasheet information:

Table is From here

enter image description here

I'm worried about max input current Iin that datasheet tables tell us to be 0.1uA.

  1. Does it means that I must be limiting the input current to this value: 0.1uA?

  2. I have been testing my logic function. As max Vin = 12V, I put a serial resistor between 12V pin and logic gate input pin. So current will be limited to R = 12V/I. I test different values for R allowing to work with 2mA, 1mA and 0.6mA and application stills working normally during the tests time. But I wondered if the correct way is to get Iin less than 0.1uA. So this means a too much bigger resistor value, more than 20 megaOhms! Has this approach any sense? Please if my argumentation is wrong let me know.

  3. Taking datasheet and calculations into account; what input current value would you allowing to be driven through input pin? What resistor value would you choose?

NOTE: I have chosen this Texas Instruments families looking for family that allows working with 12V control signals at their inputs and their outputs as high state. I also choose devices that have more than one gate. I will use these outputs for activate reed relays, but I will connect the outputs to a driver, and driver outputs go to the coil relays (concretely to the coil negative terminal). Image is from CD4073B and CD4081B datasheet. Datasheet here

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  • \$\begingroup\$ What they said. But, why not specify which logic series you are concerned with, and say why you chose that logic family. As explained, there should not be a problem BUT if people know what you are doing and are not just asked to work with a subset of relevant information they can help much more. \$\endgroup\$ – Russell McMahon Oct 9 '19 at 20:07
  • \$\begingroup\$ @RussellMcMahon thank you for the suggestion. I have chosen this Texas Instruments product looking for families that allows working with 12V control signals at their inputs and their outputs as high state. I also choose devices that have more than one gate. I use these outputs for activate reed relays, but I will connect the outputs to a driver, and driver outputs go to the coil relays (concretely to the coil negative terminal). Image is from CD4073B and CD4081B datasheet. \$\endgroup\$ – Suvi_Eu Oct 10 '19 at 7:57
  • \$\begingroup\$ Thanks for the edit. I've added a datasheet link to your answer. Others have covered this, but in summary - the CD series CMOS gate have amongst the lowest static current drains of any available. I say "among" as the CD series are "buffered" gates with higher (but still very low) current drain and greater drive than the original CMOS families such as the 74Cxxx ICs. These are no considered obsolete and the buffered ICs are suitable for essentially any task where general purpose CMOS is appropriate. \$\endgroup\$ – Russell McMahon Oct 10 '19 at 15:52
  • \$\begingroup\$ Adding series input resistors to logic gates is usually a bad or very bad idea. Apart from the leakage currents the 'pullup' resistors will draw minimal current when the switches are O/C as the drop across the resistors will be close to zero. If minimum possible current is absolutely essential then using SPDT switches rather than SPDT, connecting the gate input to the switch common terminal and perhaps adding a pullup to the pin will help. || Pullups of 10 megohm are acceptable in clean dry (or well conformally coated) conditions. Do note the effect of leakage current flow in pullup resistors \$\endgroup\$ – Russell McMahon Oct 10 '19 at 15:59
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    \$\begingroup\$ I have rearranged your question and added some information from your comments. I believe that the question now conveys your main requirement first, and then raises issues that are based on misunderstandings. The two answers so far are correct but tend to mislead you by addressing aspects that you did not directly ask about. \$\endgroup\$ – Russell McMahon Oct 11 '19 at 8:22
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You are mixing up two sets of ratings. The table part of the data sheet is showing the maximum input current you could expect to see if the part was powered from an 18V supply with inputs in a normal range within the supply voltage levels. In fact for that test case the input was set at 0.18V. This current spec is really a leakage current which is mostly due to the input protection diodes on the part that will have more leakage as the voltages increase.

The MAXIMUM rating section where it shows the +10/-10mA input current limits is what the manufacturer says is the maximal current on a single input that can be allowed before the part becomes non-functional. This will only likely ever occur if the input protection diodes on the chip start to become forward biased (i.e. the input voltage approaching VDD+0.5V or GND-0.5V).

If your system design is such that you can assure that your inputs to the logic device will stay within the power supply voltage range then there should be no need to put resistors in series with the inputs to the chip. On the other hand if your inputs may have a tendency to go outside the supply voltage range by more than a few tenths of a volt then you will want take steps to protect the chip. One way is to design the input signals with clamping circuitry that keeps the signal levels from going too high above VDD or too far below GND. The other thing that can be done is to add series resistors such as you are asking about. The resistor value that you select will depend how much the input signals disobey the supply voltage levels. The selected resistor needs to make sure to limit current into the forward biased input protection diodes on the chip. Clearly the best is to limit to less than the +10/-10mA maximal spec. A good operating choice may be +1/-1mA.

The series resistors can be a disadvantage for some applications where the chip is used for high frequency signalling. The inputs to these chips exhibits some capacitance and the series resistor forms an RC circuit which slows down the signal arriving at the chip.

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  • \$\begingroup\$ I guessed that max rating is before to be broken/unfunctional. You are right about the Vin = 0.18V test condition. The other question that you are telling me is about if my input voltage is kept inside this range VDD+0.5V or GND-0.5V diodes should not become forward biased. I also need the resistors for making the pull up inputs and not having high impedance states there (at gates inputs). I also have chosen 1mA current limitation. So when Vin = GND, current will drive from 12V node through resistor. I guess this inverse current (orange narrows) doesn' t affect those diodes. \$\endgroup\$ – Suvi_Eu Oct 9 '19 at 13:54
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First of all, the "Absolute Maximum" rating of ±10 mA refers to the amount of current you can force through the input protection diodes without physically destroying them — i.e., by forcing the input voltage to a value outside the supply rails. If your inputs can do that, you'll need to have series resistors to limit the current.

Note that current levels that don't destroy the device can still disrupt its operation by introducing current into the chip substrate that shouldn't be there. In the worst case, this can cause "latch-up", in which the chip essentially shorts its own power supply to ground through a parasitic SCR structure. If the supply current isn't limited, this can destroy the chip, too.

Therefore you want to stay well away from forcing any significant current through those protection diodes. The best way to do that is to use external Schottky diodes as clamps (they have a lower forward voltage drop than the on-chip diodes), along with a current-limiting series resistor that protects those external diodes from overcurrent.

For example, if this is an automotive/industrial application that could see ±200 V transients on the inputs, and you want to limit the input current to 1 mA, then you would need to use series resistors of

$$\frac{200\text{ V}}{1\text{ mA}} = 200\text{ kΩ}$$


The other specification (±0.1 µA) is for "leakage current". The CMOS inputs nominally draw zero current, since they're essentially the gates of MOSFETs. But the input protection circuitry can have a certain amount of current flowing through it during normal operation, and the datasheet is telling you that it won't be any higher than ±0.1 µA.

You don't need to externally limit the current to that value; the device does it itself. But it does put an upper limit on the size of pullup and pulldown resistors you can use — they need to be able to pass that amount of current while still maintaining the correct logic voltage level. For example, if you want your pullup/pulldown to drop no more than, say, 2 V, then its value can be no larger than

$$\frac{2\text{ V}}{0.1\text{ µA}} = 20\text{ MΩ}$$

Other factors (e.g., switching speed) will typically dictate lower values than this anyway.

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  • \$\begingroup\$ Hi @Dave Tweed, I got it, so my value calculation is the upper limit value instead de minimum one that I need. Thanks for this clarification so it has really been useful. I will be thinking about Shottky diodes too. \$\endgroup\$ – Suvi_Eu Oct 10 '19 at 8:56

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