We're working with a ADC chip test setup that uses the TXDB0108 to step up 1.8V data lines to 2.5V that are connected to Kintex7 FPGA.
The pin-out is as follows:
VCCA is 1.8V, while VCCB is on a 2.5V rail.There are series resistor (value 10 ohm) on each of the data lines on both sides of the level translator.
The sample rate of the ADC chip under test is 2.5MSPS. OE is pulled up to VCCA through a 10 K Ohm resistor. We have 0.1uF bypass capacitors on both supplies. The issue that we are currently facing is that whenever ADC starts conversion and the data is available on the lines we observe high frequency noise that gets coupled to the supply. When there is no data on the channels of the level translator we do not see this noise. To confirm if this noise is coming from the ADC or from the level translator we disconnected the chip board of ADC and supplied a square wave to one of the channels. The frequency of the signal was 2.5MHz and we observed the same noise pattern on the data lines and the supply.
In this image channel 1 is the 2.5MHz signal at the B side of the channel of the level translator and channel 2 is VCCA of the level translator which is 1.8V. We are observing oscillations in the signal.
The image below has channel 1 showing the A side of the channel of level translator which is the supplied 2.5MHz signal from a source and channel 2 showing the VCCB of the level translator which is 2.5V. The noise appears on both supplies as well.
As you can see there is significant noise that appears on the signal which is getting coupled to the DC supply.
Now we had previously installed 0.1uF bypass caps close to the level translator for proper operation but after observing this noise we soldered 10nF in addition to the 0.1uF caps. To our disappointment there was no improvement seen.
We need your help to remove this noise as this is reducing the SNR of the ADC chip. Please let us know if you need any more information. Urgent help would be appreciated.