I have three switching regulators. A 12V, 5V(green box), and 48V(purple box). The plan is to supply both regulators through -/+12vout pours.

If I am trying to minimize board size while also minimizing EMI, what is the best strategy for laying out these regulators?

If I pack the components as much as I can, what will the consequences be?

A professional perspective on how power should be routed to the green and purple regulators would be highly appreciated. Lastly, any criticism of current design is extremely valuable to me.

*Board stack up is 6 layers with L2 & L5 as GND Layers.

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    \$\begingroup\$ First off, follow the respective datasheets for these switcher layouts. Most datasheets have very specific layout recommendations. Second, be very careful on where the power inductors (and switching nodes) end up in terms of proximity to other sensitive victim components. \$\endgroup\$ – Steve Oct 9 '19 at 17:33
  • \$\begingroup\$ @Steve I have followed both datasheet recommendations and reference designs to get to this layout. (green and purple regulators have not been wired yet tho) What characterizes a sensitive victim component? and what is a good a good distance to keep between power inductors/nodes and sensitive components? \$\endgroup\$ – circuit_noob533 Oct 9 '19 at 17:40
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    \$\begingroup\$ One such sensitive component/circuit would be the feedback loops on each of the switchers or other nets that are not shown, perhaps isolation paths or inputs to other digital devices. Distance would be like 50 mils or so, just be aware of these gotchas. If you have the real estate use where it make most sense. \$\endgroup\$ – Steve Oct 9 '19 at 18:01

If I pack the components as much as I can, what will the consequences be?

The parasitic resistance and inductance between components will go down, this will lead to less loss in traces and slightly better performance.

The thermal resistance between components will also go down, because there is less copper separating components, leading to more heat from components on less area of the board, and the heat from components affecting other components

In other words, you need to find out how much power is being dissipated in both regulators, and do a thermal analysis on the PCB (usually done with FEM software). In the least you need to know how many watts of heat are going into the PCB and space hot components away from each other.

You should be fine on EMC if you follow the recommended layout patterns of manufacturers. They usually also post results of EMC on eval boards so you should expect similar results with the same layout.

  • \$\begingroup\$ I have never done a PCB FEM analysis, do you happen to know of any resources that could help me put together a heat analysis simulation? and/ or what the workflow should look like? I am guessing I need to export the PCB to some sort of CAD software and then go from there? \$\endgroup\$ – circuit_noob533 Oct 9 '19 at 18:34
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    \$\begingroup\$ If you have altium, they have a tool for 2k$ that you can buy, if not things get expensive. There are a lot of third party tools, and some very expensive tools like ANSYS. There are some free tools, but you can burn a lot of time getting them to work. I prefer building and testing, because 1 revision of a board takes less time and money than FEM (although the altium tool is probably worth it). At minimum I would calculate the wattage and make sure anything over 5W on the PCB isn't too close to other heat sources. \$\endgroup\$ – Voltage Spike Oct 9 '19 at 18:53

Lets predict how inductive switching fields might trash your feedback node.

Assume 1 amp in 10 nanoseconds, being switched 1mm away from the feedback node, and assume the feedback node (plus the GND return) forms a 1mm by 1mm loop.

How much trash gets induced into your feedback signal?

We use Vinduce = [ MUo * MUr * Area / (2 * PI * distance)] * dI/dT

(And we ignore some natural_log terms)

With MUo = 4*pi*1e-7, and MUr = 1 (for air, FR-4, copper), the Vinduce becomes

Vinduce = [ 2e-7 * Area/Distance ] * dI/dT

Filling in the variables, we have

Vinduce = [ 2e-7 * (1mm * 1mm)/1mm] * 10^8 amp/second

Vinduce = 2e-7 * 1mm * 1e+8 = 2*10^(-7 -3 +8) = 2*10^-2 = 0.02 volts.

Will 20 milliVolts, lasting for the high-current edge-event, be a problem?

  • \$\begingroup\$ Would the 20mV be seen by the controller? And would that, in turn, change the output? \$\endgroup\$ – circuit_noob533 Oct 11 '19 at 15:10
  • \$\begingroup\$ what is your feedback node DC_voltage? 1.25 volts (approximately a bandgap voltage?) The example I showed, which produces 20 milliVolts in series with the feedback voltage but only lasts for 10 nanoseconds, is very dependent upon the actual circuit, the actual slewrates, the actual current being switched, and the ACTUAL PCB LAYOUT. A 10 nS pulse might make any regulator ring. Or maybe not. Just be aware. Test your circuit, by injecting a 20 millivolt upset. \$\endgroup\$ – analogsystemsrf Oct 12 '19 at 3:48

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