Output on Pass-transistor NAND gate lower than expected

I have an assignment to design an IC NAND gate, consisting og 2 NMOS-transistors and a designed inverter as seen in figure 1 and 2.

But when measuring the output at Vout, we only get about 60% of the expected value, which would be 1.5V. I can't figure out the issue.

Edit:

I am trying to design my NAND gate according to figure 4. Our goal is to keep the output at the same level as the input while still holding the true to the truth table Edit 2

Another suggestion from a group doing the same course, was to make an AND gate and placing an inverter at the output.

Settings:

VDD = 1.5V

Vin_A:

• Amplitude = 0 - 1.5 V
• Period = 2 ns
• Rise Time = 0.1 ns
• Fall Time = 0.1 ns
• Pulse Width = 1 ns
• Delay = 0 ns

Vin_B:

• Amplitude = 0 - 1.5 V
• Period = 2 ns
• Rise Time = 0.1 ns
• Fall Time = 0.1 ns
• Pulse Width = 1 ns
• Delay = 0.5 ns

Figures

• Are you required to use this design with the 2 NMOS transistors? A normal CMOS NAND gate would probably be better in most respects. If you need to keep it like this, can you add PMOS transistors in parallel with the NMOS ones so you create full transmission gates? That's actually a common way to make XOR gates. – Justin Oct 9 at 17:48

The sources of your two NMOS transistors are connected to the NAND gate output, so the NAND gate output (the sources) must be at a lower voltage than the transistor gates when the transistors are conducting. If the highest voltage in your circuit is 1.5V, and you drive the transistor gates to 1.5V, then the NMOS transistors can not bring the NAND output voltage any higher than (approximately) $$\1.5\,\mathrm{V}-V_{THN}\$$