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I have an assignment to design an IC NAND gate, consisting og 2 NMOS-transistors and a designed inverter as seen in figure 1 and 2.

But when measuring the output at Vout, we only get about 60% of the expected value, which would be 1.5V. I can't figure out the issue.

Edit:

I am trying to design my NAND gate according to figure 4. Our goal is to keep the output at the same level as the input while still holding the true to the truth table

enter image description here

Edit 2

Another suggestion from a group doing the same course, was to make an AND gate and placing an inverter at the output.

Settings:

VDD = 1.5V

Vin_A:

  • Amplitude = 0 - 1.5 V
  • Period = 2 ns
  • Rise Time = 0.1 ns
  • Fall Time = 0.1 ns
  • Pulse Width = 1 ns
  • Delay = 0 ns

Vin_B:

  • Amplitude = 0 - 1.5 V
  • Period = 2 ns
  • Rise Time = 0.1 ns
  • Fall Time = 0.1 ns
  • Pulse Width = 1 ns
  • Delay = 0.5 ns

Figures

enter image description here [Figure 1]

enter image description here [Figure 2]

enter image description here [Figure 3]

enter image description here [Figure 4]

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  • \$\begingroup\$ Are you required to use this design with the 2 NMOS transistors? A normal CMOS NAND gate would probably be better in most respects. If you need to keep it like this, can you add PMOS transistors in parallel with the NMOS ones so you create full transmission gates? That's actually a common way to make XOR gates. \$\endgroup\$ – Justin Oct 9 at 17:48
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Remember that for an NMOS transistor to conduct you must bring the gate voltage above the source voltage, and we usually expect the difference to be at least equal to the transistor's threshold voltage if want significant current.

The sources of your two NMOS transistors are connected to the NAND gate output, so the NAND gate output (the sources) must be at a lower voltage than the transistor gates when the transistors are conducting. If the highest voltage in your circuit is 1.5V, and you drive the transistor gates to 1.5V, then the NMOS transistors can not bring the NAND output voltage any higher than (approximately) \$1.5\,\mathrm{V}-V_{THN}\$

EDIT, after Figure 4 was added:

You can't do this with real transistors. The source voltage for an NMOS must be lower than the gate when the transistor is conducting. If you try to manipulate the transistor threshold closer to 0V (either with a body bias or by changing the doping) then the transistor will not turn off properly, and subthreshold leakage will make it impossible to get a proper 0 logic level. That's why pass transistor logic is so rarely used.

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  • \$\begingroup\$ Yeah, i thought so too. Our assignment involved two approaches. 1 with complementary CMOS and the second is the pass-transistors as you see. So i was looking for suggestion to maybe fix this issue or another approach while still containing the figure 4 circuit @Justin's suggestion would be to add PMOS transistors in parallel to meet our goal. \$\endgroup\$ – Vinh Trung Thai Oct 9 at 20:26

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