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My lecturer gave us the following problem today:

"A CMOS gate (with inputs A, B, C) consists of a pull-up network with 0 or more PMOS transistors, and a pull-down network with 0 or more NMOS transistors. The output is \$ f(A,B,C)\$. The truth table for \$ f(A,B,C) \$ has both 0's and 1's as outputs.

What is \$ f(1,1,1) \$?"

My initial thought was that \$ f(1,1,1) = 0 \$ since the PMOS transistors would be open (so that current can't run through) while the NMOS transistors would be closed and allowed a current through to GND resulting in a low output.

But since I don't know the actual boolean expression of \$ f(A,B,C) \$ can I really be sure this is the case?

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    \$\begingroup\$ "But since I don't know the actual boolean expression " So then why don't you come up with the boolean expression? Sounds to me like you might be a little bit stuck in some sort of student mindset. There's nothing different about the problem just because the prof named the result F(A,B,C). If he instead just said, what is the output when all the inputs are 1, would you still be asking the same question? \$\endgroup\$ – DKNguyen Oct 9 '19 at 19:29
  • \$\begingroup\$ How am I supposed to do that? Theoretically the circuit could consist of hundreds of transistors. \$\endgroup\$ – Carl Oct 9 '19 at 19:32
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    \$\begingroup\$ There is a subtle but important bit of language in the question...you have a pullup network and a pulldown network. This implies to me a gate with a single logic level. \$\endgroup\$ – Elliot Alderson Oct 9 '19 at 19:40
  • \$\begingroup\$ So then make a few circuits and boolean expressions with different numbers of transistors and see if there's a pattern. You could go so far as to actually prove it out to an infinite number of transistors if you felt like it. Just like many math proofs. Is the result any different if two logical ones are OR'd together? Three? A thousand? An infinite number? I know you wouldn't think there's no way to really know the result of an arbitrary number of logical ones that have been OR'd together just because each boolean expression has a different number of terms. So why would you think that here? \$\endgroup\$ – DKNguyen Oct 9 '19 at 19:46
  • \$\begingroup\$ Suppose there are 0 PMOS transistors and 0 NMOS transistors and the "logic function" is just a wire between input B and the output? \$\endgroup\$ – The Photon Oct 9 '19 at 22:25
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Your thought is exactly correct.

The reasoning goes like this: The simplest possible CMOS gate has one pullup and one pulldown, and it functions as an inverter.

You can add additional pullup and pulldown transistors to the gate, but all they can do is form non-inverting AND and OR functions in conjunction with whatever is already there. Therefore any arbitrary CMOS gate is some function consisting only of ANDs and ORs, followed by an inverter.

Furthermore, in CMOS, the pulldown network must be the logical "dual" of the pullup network. If there are transistors in series (AND function) in the pulldown network, there must be a corresponding set of transistors in parallel (OR function) in the pullup network, and vice-versa.

So in the end, any arbitrary function consisting only of AND and OR operations, given an input of all-ones, must have a result that is 1. And then the inversion makes that a 0. QED!

BTW, any CMOS gate that has 3 inputs must have at least three pullups and three pulldowns, otherwise at least one of the inputs does nothing at all. The "zero or more" is a red herring.

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  • \$\begingroup\$ Well I wasn't going to just give away the answer... \$\endgroup\$ – Elliot Alderson Oct 9 '19 at 20:20
  • \$\begingroup\$ @ElliotAlderson: The OP already has the answer, and is just looking for confirmation. As I indicated with my very first statement. \$\endgroup\$ – Dave Tweed Oct 9 '19 at 20:21
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The important part of the question is the wording that you have "A [single] gate" with "a [single] pullup network...of PMOS" and "a [single] pulldown network...of NMOS". That greatly restricts the kinds of gates that you need to consider. For example, you can't make an XOR gate fit this definition.

So, think about what kinds of individual gates can be built in this style what the output would be for \$f(1,1,1)\$.

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  • \$\begingroup\$ Okay so if I understand this correctly. The reason the XOR gate doesn't fit the definition, is because it consists of more than 1 pull-up/down network? Like it is shown in this picture? google.com/… \$\endgroup\$ – Carl Oct 9 '19 at 19:52
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    \$\begingroup\$ @Carl Elliot is trying to hint to you that the prof has described exactly what logic gate it is (at least for the only input combination he seems to care about), and that it doesn't matter how many pull-down (or pull-down) transistors you have in parallel if they all share the same drive signal. The result is still the same. You already have an image of what it is in your mind of what the circuit looks like, even with a variable number of transistors. Try drawing it out with different numbers of PMOS and NMOS, but instead of A, B, C, just use 1s since that's the problem wants \$\endgroup\$ – DKNguyen Oct 9 '19 at 20:01
  • \$\begingroup\$ @Carl Yes, the XOR gate requires multiple primitive CMOS gates to implement. \$\endgroup\$ – Elliot Alderson Oct 9 '19 at 20:21

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