# Implementing 4-bit counter on GAL 16V8

I want to use a GAL 16V8 to implement a 4-bit counter using Verilog. I'm using Lattice's ispLEVER software.

So far I have had no issues using Verilog to implement combinational logic.

However, I am unable to implement sequential logic. My logic probe registers the clok signal fine (coming from TTL function generator, HIGH/LOW at ~1 Hz), the output signals (a,b,c,d) read HIGH on my logic probe when disconnected, and high-Z when connected to output LEDs.

How do I edit my Verilog code to make this work as a counter?

My Verilog code:

module counter(clok, a,b,c,d);
input clok;
output reg a, b, c, d;

always @(posedge clok) begin
d <= ~d;
c <= c ^ d;
b <= ~b&c&d | b&~c | b&~d;
a <= ~a&b&c&d | a&~b | a&~c | a&~d;
end
endmodule


GAL chip report:

Page 1 ispLEVER Classic 2.0.00.17.20.15 - Device Utilization Chart
Fri Oct 11 10:44:26 2019

Module : 'counter'

Input files:

ABEL PLA file        : untitled.tt3
Device library       : P16V8R.dev


Output files:

Report file          : untitled.rpt


Page 2 ispLEVER Classic 2.0.00.17.20.15 - Device Utilization Chart
Fri Oct 11 10:44:26 2019

## P16V8R Programmed Logic:

b.D   = (  !b.PIN & !c.PIN
#   b.PIN & c.PIN & d.PIN
#   !b.PIN & !d.PIN ); " ISTYPE 'INVERT'
b.C   = (  clok );

a.D   = (  !a.PIN & !b.PIN
#   !a.PIN & !c.PIN
#   a.PIN & b.PIN & c.PIN & d.PIN
#   !a.PIN & !d.PIN ); " ISTYPE 'INVERT'
a.C   = (  clok );

d.D   = (  d.PIN ); " ISTYPE 'INVERT'
d.C   = (  clok );

c.D   = (  c.PIN & d.PIN
#   !c.PIN & !d.PIN ); " ISTYPE 'INVERT'
c.C   = (  clok );


Page 3 ispLEVER Classic 2.0.00.17.20.15 - Device Utilization Chart
Fri Oct 11 10:44:26 2019

## P16V8R Chip Diagram:

                                P16V8R

+---------\       /---------+
|          \     /          |
|           -----           |
clok |  1                    20  | Vcc
|                           |
|  2                    19  |
|                           |
|  3                    18  |
|                           |
|  4                    17  |
|                           |
|  5                    16  |
|                           |
|  6                    15  | !c
|                           |
|  7                    14  | !d
|                           |
|  8                    13  | !a
|                           |
|  9                    12  | !b
|                           |
GND | 10                    11  |
|                           |
|                           |
---------------------------'

SIGNATURE: N/A


Page 4 ispLEVER Classic 2.0.00.17.20.15 - Device Utilization Chart
Fri Oct 11 10:44:26 2019

## P16V8R Resource Allocations:

        Device        | Resource  |   Design    |
Resources      | Available | Requirement | Unused
======================|===========|=============|==============
|           |             |  Input Pins:           |           |             |
|           |             |
Input:      |     10    |      1      |    9 ( 90 %)
|           |             |  Output Pins:          |           |             |
|           |             |
In/Out:     |      8    |      4      |    4 ( 50 %)
Output:     |      -    |      -      |    -
|           |             |  Buried Nodes:         |           |             |
|           |             |
Input Reg:  |      -    |      -      |    -
Pin Reg:    |      8    |      4      |    4 ( 50 %)
Buried Reg: |      -    |      -      |    -


Page 5 ispLEVER Classic 2.0.00.17.20.15 - Device Utilization Chart
Fri Oct 11 10:44:26 2019

## P16V8R Product Terms Distribution:

          Signal           |    Pin   | Terms | Terms | Terms
Name            | Assigned | Used  |  Max  | Unused
===========================|==========|=======|=======|=======
b.D                        |   12     |   3   |   8   |   5
a.D                        |   13     |   4   |   8   |   4
d.D                        |   14     |   1   |   8   |   7
c.D                        |   15     |   2   |   8   |   6

==== List of Inputs/Feedbacks ====

Signal Name                      | Pin      | Pin Type
=================================|==========|=========
clok                             |    1     | CLK
a.PIN                            |   13     | COMB FB
b.PIN                            |   12     | COMB FB
c.PIN                            |   15     | COMB FB
d.PIN                            |   14     | COMB FB


Page 6 ispLEVER Classic 2.0.00.17.20.15 - Device Utilization Chart
Fri Oct 11 10:44:26 2019

## P16V8R Unused Resources:

Pin  |  Pin  |   Product  | Flip-flop Number |  Type  |   Terms  |   Type
=====|========|=============|==========
2  |  INPUT |      -      |    -
3  |  INPUT |      -      |    -
4  |  INPUT |      -      |    -
5  |  INPUT |      -      |    -
6  |  INPUT |      -      |    -
7  |  INPUT |      -      |    -
8  |  INPUT |      -      |    -
9  |  INPUT |      -      |    -
16  |  BIDIR | NORMAL  7   |    D
17  |  BIDIR | NORMAL  7   |    D
18  |  BIDIR | NORMAL  7   |    D
19  |  BIDIR | NORMAL  7   |    D
`
• You should enable the counter outputs ABCD, not BIDIR but OUPUT. If you want them three state, you need a control input for these. – Uwe Oct 11 '19 at 17:57
• @jsotola thanks, edited my question to ask HOW DO I MAKE IT WORK LIKE A COUNTER – lemontwist Oct 11 '19 at 18:20
• @Uwe I want it to act like a counter... I don't want them to tri-state but they appear to be tri-stating. I don't have an output enable on my GAL. I just want it to count. It's not counting. – lemontwist Oct 11 '19 at 18:21
• You need to specify the outputs should be always enabled. See the GAL16V8 datasheet and the Verilog manual. – Uwe Oct 11 '19 at 18:25
• Do you have pin 11 connected to Ground? – Bruce Abbott Oct 11 '19 at 18:37

So far I have had no issues using Verilog to implement combinational logic... However, I am unable to implement sequential logic... the output signals (a,b,c,d) read... high-Z when connected to output LEDs

The GAL16V8 is designed to replace several different PAL (Programmable Array Logic) chips, some combinatorial and some registered. Registered PAL chips generally have an Enable pin which is used to tri-state the outputs when high.

When you create combinatorial logic the GAL is put into 'simple' or 'complex' mode where each output pin is either always active or individually controlled. When you create sequential logic the GAL is put into 'registered' mode, and then all outputs are controlled by the Enable pin. In registered mode this pin is not programmable, and must be pulled to ground externally.